Abstract
This paper presents a hardware technique to reduce of static and dynamic power consumption in FUs. This approach entails substituting some of the power-hungry adders of a 64-bit superscalar processor, by others with lower power-consumption, and modifying the slot protocol in order to issue as much instructions as possible to those low power consumption units incurring marginal performance penalties. Our proposal saves between a 2% and a 45% of power-performance in FUs and between a 16% and a 65% of power-consumption in adders.
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References
Brooks, D., Martonosi, M.: Dynamically exploiting narrow width operands to improve processor power and performance. In: Proc of the 5th Int.l Symp on High Performance Computer Architecture (HPCA), pp. 13–22 (1999)
Brooks, D., Martonosi, M.: Value-based clock gating and operation packing: dinamic strategies for improving processor power and performance. ACM Transaction on Computer Systems 2, 89 (2000)
Seng, J.S., Tune, E.S., Tullsen, D.M.: Reducing power with dynamic critical path information. In: Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, p. 114
Choi, J., Jeon, J., Choi, K.: Power minimization of functional units partially guarded computation. In: Proceedings of the 2000 international symposium on Low power electronics and design, pp. 131–136 (2000)
Chen, O.-C., Sheen, R.-B., Wang, S.: A low-power adder operating on effective dynamic data ranges. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10(4), 435–453 (2002)
Haga, S., Reeves, N., Barua, R., Marculescu, D.: Dynamic funcional unit assignment for low power. In: Design, Automation and Test in Europe Conference and Exhibition (DATE 2003), pp. 3–7 (2003)
Perelman, E., Hamerly, G., Calder, B.: Picking statistically valid and early simulation points. In: The International Conference on Parallel Architectures and Compilation Techniques (2003)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architecturallevel power analysis and optimizations. In: Proceedings of the 27th International Symposium on Computer Architecture, pp. 83–94 (2000)
Gonzlez, J., Skadron, K.: Power-aware design for high-performance processors. In: 10th International Symposium on High-Performance Computer Architecture, HPCA-10 (2004)
Gowan, M., Biro, L., Jackson, D.: Power considerations in the design of the alpha 21264 microprocessor. In: 35th Design Automation Conference (1998)
Lee, H.-H.S., Fryman, J.B., Diril, A.U., Dhillon, Y.S.: The elusive metric for low-power architecture research. In: The Workshop on Complexity-Effective Design in conjunction with ISCA-30 (2003)
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Miñana, G., Garnica, O., Hidalgo, J.I., Lanchares, J., Colmenar, J.M. (2005). Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_5
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DOI: https://doi.org/10.1007/11556930_5
Publisher Name: Springer, Berlin, Heidelberg
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