Abstract
The energy efficiency of a 0.25 μm general-purpose FIR filter design, based on two-phase clocking, versus a functionally equivalent benchmark, based on one-phase clocking, is demonstrated by means of measurements and transistor level simulations. Architectural improvements enable already a 20% energy savings of the two-phase clocking implementation. Yet, for the first time, the limitations imposed by the supply voltage (< 2.1 V) and the operating frequency (< 10 MHz) on the actual energy efficiency of this low-power strategy are investigated. Transistor level re-design is undertaken: a new slew-insensitive latch is presented and replaced inside the two-phase implementation. Spectre simulations point out the final 30% savings.
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© 2005 Springer-Verlag Berlin Heidelberg
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Carbognani, F., Bürgin, F., Felber, N., Kaeslin, H., Fichtner, W. (2005). Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_46
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DOI: https://doi.org/10.1007/11556930_46
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
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