8.1 Abstract
In this chapter we will describe a Design-for-Test (DfT) methodology for systems-on-chip. We have developed a hybrid Built-In Self-Test (BIST) approach, where the test set is assembled from pseudorandom test patterns that are generated online and deterministic test patterns that are generated offline and stored in the system. We have analyzed the aspects related to the cost calculation of such a hybrid BIST approach and will propose a test cost minimization strategy for single-core designs. We have then extended the same approach for multi-core designs and developed a test time minimization methodology under tester memory constraints. We will demonstrate the applicability and efficiency of the proposed approach for cores with different core-level DfT structures and for systems with different system-level test architectures.
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Jervan, G., Ubar, R., Peng, Z., Eles, P. (2005). An Approach to System-level Design for Test. In: Sonza Reorda, M., Peng, Z., Violante, M. (eds) System-level Test and Validation of Hardware/Software Systems. Springer Series in Advanced Microelectronics, vol 17. Springer, London. https://doi.org/10.1007/1-84628-145-8_8
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DOI: https://doi.org/10.1007/1-84628-145-8_8
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