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System-level Test and Validation of Hardware/Software Systems

  • Matteo Sonza Reorda
  • Zebo Peng
  • Massimo Violante

Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 17)

Table of contents

  1. Front Matter
    Pages i-xii
  2. Z. Peng, M. Sonza Reorda, M. Violante
    Pages 1-3
  3. J. P. Teixeira
    Pages 5-25
  4. F. Fummi, G. Pravadelli
    Pages 27-46
  5. O. Goloubeva, M. Sonza Reorda, M. Violante
    Pages 47-65
  6. G. Jervan, R. Ubar, Z. Peng, P. Eles
    Pages 67-81
  7. E. Sánchez, M. Sonza Reorda, G. Squillero
    Pages 83-106
  8. I. G. Harris
    Pages 107-120
  9. G. Jervan, R. Ubar, Z. Peng, P. Eles
    Pages 121-149
  10. A. Bobbio, D. Codetta Raiteri, M. De Pierro, G. Franceschinis
    Pages 151-174
  11. Back Matter
    Pages 175-179

About this book

Introduction

New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.

As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue.

System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:

• modeling of bugs and defects;

• stimulus generation for validation and test purposes (including timing errors;

• design for testability.

For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference.

Keywords

Hardware Microelectronics System-on-Chip Validation microprocessor modeling reliability software system system on chip (SoC) testing

Editors and affiliations

  • Matteo Sonza Reorda
    • 1
  • Zebo Peng
    • 2
  • Massimo Violante
    • 1
  1. 1.Dipartimento di Automatica e InformaticaPolitecnico di TorinoTorinoItaly
  2. 2.Department of Computer and Information ScienceLinköping UniversityLinköpingSweden

Bibliographic information

  • DOI https://doi.org/10.1007/1-84628-145-8
  • Copyright Information Springer-Verlag London Limited 2005
  • Publisher Name Springer, London
  • eBook Packages Engineering
  • Print ISBN 978-1-85233-899-2
  • Online ISBN 978-1-84628-145-7
  • Series Print ISSN 1437-0387
  • Buy this book on publisher's site