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Modeling the SOI MOSFET nonlinearities. An empirical approach

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TRANSISTOR LEVEL MODELING FOR ANALOG/RF IC DESIGN

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Author information

Authors and Affiliations

  1. Microwave Laboratory – Place du Levant, 3, Université catholique de Louvain (UCL), B-1348, Louvain-la-Neuve, Belgium

    B. Parvais

  2. ANODE group, IEMN, Avenue Poincaré, 60069, 59652, CNRS, UMR 8520, Villeneuve d'Ascq, France

    A. Siligaris

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  1. B. Parvais
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Editors and Affiliations

  1. Freescale, Switzerland

    WLADYSLAW GRABINSKI

  2. Belgium

    BART NAUWELAERS

  3. Kasteelpark Arenberg 10, 3001, Leuven, Belgium

    DOMINIQUE SCHREURS

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Parvais, B., Siligaris, A. (2006). Modeling the SOI MOSFET nonlinearities. An empirical approach. In: GRABINSKI, W., NAUWELAERS, B., SCHREURS, D. (eds) TRANSISTOR LEVEL MODELING FOR ANALOG/RF IC DESIGN. Springer, Dordrecht. https://doi.org/10.1007/1-4020-4556-5_6

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  • DOI: https://doi.org/10.1007/1-4020-4556-5_6

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-1-4020-4555-4

  • Online ISBN: 978-1-4020-4556-1

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