Multiband Broadband Modulator Implementation on Field-Programmable Gate Array

  • Cristhian Castro
  • Carlos GordónEmail author
  • Patricio Encalada
  • Myriam Cumbajín
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 1195)


The proper management of resources available in FPGA’s is one of the main issues that designers must consider when implementing a high bandwidth communications system. For this reason, we report the hardware-efficient implementation, for mapping stages and pulse shaping, of broadband multi-level QAM signals, in Field-Programmable Gate Array (FPGA) devices. The process for designing the system is based on the large capacity of analog-digital (ADC) converters that exist today, in this case the ADC has a sampling rate of 5 GSPS, which allows the transmission of signals with bandwidths of about 2.5 GHz. The model implements in the same polyphase FIR structure multiplier-less the mapping schemes Q-PSK, 16-QAM, 64-QAM y 256-QAM together with the RRC filter. As a result, this implementation shows that the proposed architecture eliminates the use of dedicated multipliers which would be around 3150 if conventional methods were used. The Error Vector Module is used as a figure of merit in the selection of the RRC filter and the digital quantization levels. We achieved the target frequency for hardware operation at 312.5 MHz con un factor de interpolation de 16 and an EVM < 2%. Also, Hardware Description Language (HDL) models are validates in test benches with reference to the finite precision models of Simulink.


RRC FPGA Polyphase structures Digital modulation Multiplier less FIR HDL 



The authors thank the Technical University of Ambato and the “Dirección de Investigación y Desarrollo” (DIDE) for their support in carrying out this research, in the execution of the project “Plataforma Móvil Omnidireccional KUKA dotada de Inteligencia Artificial utilizando estrategias de Machine Learning para Navegación Segura en Espacios no Controlados”, project code: PFISEI27.


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Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Universidad Politécnica de ValenciaValenciaSpain
  2. 2.Facultad de Ingeniería en Sistemas, Electrónica e IndustrialUniversidad Técnica de Ambato, UTAAmbatoEcuador
  3. 3.Facultad de Ingeniería MecánicaEscuela Superior Politécnica de Chimborazo ESPOCHRiobambaEcuador
  4. 4.Facultad de Ingeniería y Tecnologías de la Información y la ComunicaciónUniversidad Tecnológica Indoamérica, UTIAmbatoEcuador

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