Abstract
This chapter focuses on the reliability of a specific class of systems on chip which are able to be reconfigured dynamically and partially. The possibility of using their Partial Dynamic Reconfiguration (PDR) capability for hardening applications on FPGAs is explored. We propose the use of checkpoint approaches and context restoration for tolerance against transient faults. PDR is used for managing the context of hardware tasks present on the application. The use of PDR reduces changes to the original system and therefore the complexity of the resulting system. After identifying the limitations of the “Backward Error Recovery” approach into SRAM-based FPGAs platforms, we propose a new resource placement algorithm on FPGA to minimize the access time needed by check-pointing and rolling back operations of hardware tasks. The evaluation of the overall reliability of this approach is achieved through fault injection campaigns on a demonstration platform running on a Virtex-5 that integrates the proposed reliability controller and hosts a data encryption application.
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Ghaffari, F., Romain, O., Granado, B. (2019). Mitigation Transient Faults by Backward Error Recovery in SRAM-FPGA. In: Velazco, R., McMorrow, D., Estela, J. (eds) Radiation Effects on Integrated Circuits and Systems for Space Applications. Springer, Cham. https://doi.org/10.1007/978-3-030-04660-6_10
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