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Keywords
Table of contents (8 chapters)
Reviews
From the reviews:
"This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. … The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)
Authors and Affiliations
Bibliographic Information
Book Title: Verification by Error Modeling
Book Subtitle: Using Testing Techniques in Hardware Verification
Authors: Katarzyna Radecka, Zeljko Zilic
Series Title: Frontiers in Electronic Testing
DOI: https://doi.org/10.1007/b105974
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer Science+Business Media Dordrecht 2003
Hardcover ISBN: 978-1-4020-7652-7Published: 30 November 2003
Softcover ISBN: 978-1-4419-5402-2Published: 07 December 2010
eBook ISBN: 978-0-306-48739-2Published: 17 December 2005
Series ISSN: 0929-1296
Edition Number: 1
Number of Pages: XV, 216
Topics: Robotics and Automation, Circuits and Systems, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design, Artificial Intelligence