Abstract
For the last four decades, the feature sizes of electronic devices for computers have been reduced by a factor of two roughly every 18 months. The result has been a tremendous increase in computational power and reduction in the cost of computing, as measured by cost per function, of nearly 30% annually, so that computations can be done for a billionth of the cost of using the technology of the 1950s. However, devices will soon be so small that the current technology used to produce them will have reached its limits, and the graininess of individual atoms will affect their behavior. This issue focuses on techniques to make tiny devices with dimensions under 45 nm (45 billionths of a meter) for the next generation of devices.Techniques start with coupling currently used 193-nm and 157-nm optical lithography with liquid immersion to reduce the effective wavelength. Other techniques include microprinting, self-assembly, templating, and using supercritical fluids to avoid the effects of surface tension while enabling solution-based processing at such small dimensions. The development of three-dimensional structures that are approaching this scale is also discussed.The methods presented will have an effect on many areas of technology, including, in addition to electronics, advanced sensor technology, energy conversion, catalysis, and nanoelectromechanical systems.
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References
International Technology Roadmap for Semiconductors (ITRS) Update, www.itrs.net/Common/2004Update/2004Update.htm (accessed November 2005).
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Watkins, J.J., Bishop, D.J. Fabrication of Sub-45-nm Structures for the Next Generation of Devices: A Lot of Effort for a Little Device. MRS Bulletin 30, 937–941 (2005). https://doi.org/10.1557/mrs2005.246
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DOI: https://doi.org/10.1557/mrs2005.246