Gate Current Modeling for Insulating Gate III-N Heterostructure Field-Effect Transistors

Abstract

Gate current plays an important role in determining the characteristics and limiting performance of GaN-based field effect transistors. In GaN-based HFETs, the gate current limits the gate voltage swing and, hence, the maximum device current. Since the electron transport across the wide band gap barrier layer involves trapping, under certain bias conditions, the gate current leads to the threshold voltage shifts and causes reliability problems. Under reverse bias, the gate leakage in GaN-based HFET dominates the minimum (pinch-off) drain current. Insulating gate HFETs (i.e. Metal Oxide Heterostructure Field Effect Transistors – MOSHFETs) have the gate leakage currents 4 – 6 orders of magnitude lower than HFETs, even at elevated temperatures up to 300 °C. In this paper, we report on the gate current characteristics in these devices at room and elevated temperatures. We propose a semi-empirical model for the current-voltage characteristics in these devices, which is in good agreement with experimental data. Our data also show that both tunneling and temperature activation are important factors in MOSHFETs. These results are important for possible applications of GaN MOSHFETs in high power amplifiers and power switches as well as in non-volatile memory devices and integrated circuits that will operate in a much wider temperature range than conventional silicon and GaAs devices.