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A Generalized Analytical Approach to Model the Gate Tunneling Current in Nanoscale Double Gate MOSFETs

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Abstract

An analytical model for gate tunneling current in a nanoscale double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) has been developed. The model is simple and generalized one and is based on our earlier work on gate tunneling current in single gate MOSFET, i.e., treating the band profile in the channel as a triangular potential well. The potential distribution in the silicon body is determined through a perturbation approach which facilitates analytical solution to Poisson’s equation considering the contributions from both inversion and depletion charges. Looking at the dimension of the MOSFET apart from electrical confinement the effect of structural confinement has also been taken into account. The estimated tunneling current density in the present model compares well with the results of L. Chang et al.

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References

  1. Ferain I, Colinge CA, Colinge J-P (2010) Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature 410:310–316

    Google Scholar 

  2. Balestra F, Cristoloveanu S, Benachir M, Brini J, Elewa T (1987) Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance. IEEE Electron Device Lett EDL-8(9):410–412

    Article  CAS  Google Scholar 

  3. Taur Y (Dec.2001) Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs. IEEE Trans Electron Devices 48(12):2861–2869

    Article  CAS  Google Scholar 

  4. Song J, BoYu YY, Taur Y (2009) A review on compact modeling of multiple-gate MOSFETs. IEEE Trans Circ Syst—I: Regular Papers 56(8):1858–1869

    Google Scholar 

  5. Frank DJ, Laux SE and Fischetti MV (1989) “Monte Carlo Simulation of a 30 nm Dual-Gate MOSFET: How Short Can Si Go?,” IEEE proceedings of IEEE International Electron Device Meeting, San Francisco, CA, USA, 3–6 Dec. pp.553–556,

  6. Taur Y (2000) An analytical solution to a double-gate MOSFET with Undoped body. IEEE Electron Device Lett 21(5):245–247

    Article  CAS  Google Scholar 

  7. Sarkar D, Datta D, Dasgupta S (Feb. 2008) Modeling of leakage current mechanisms in nanoscale DG MOSFET and its application to low power SRAM design. J Comput 3(2):37–47

    Article  Google Scholar 

  8. Mukhopadhyay S, Kim K, Te Chuang C, Roy K (Oct. 2006) Modeling and analysis of leakage currents in double-gate technologies. IEEE Trans Comput-Aided Design Integrated Circuits Syst 25(10):2052–2061

    Article  Google Scholar 

  9. Dubey S, Tiwari PK, and Jit S (2010) “A two-dimensional model for the potential distribution and threshold voltage of short-channel double-gate metal-oxide-semiconductor field-effect transistors with a vertical Gaussian-like doping profile”. J Appl Phys 108: 034518–7,

  10. Ieong M (2004) Silicon device scaling to the Sub-10-nm regime. Science 306(5704):2057–2060

    Article  CAS  Google Scholar 

  11. Madhu K, Prasad B, Chatterjee AK (2016) Gate tunneling current model for nanoscale MOSFETs with varying surface potential. IETE J Res 62(3):347–355

    Article  Google Scholar 

  12. Maserjian J (1974) “Tunneling in thin MOS structures”. J Vacuum Sci Technol. 11: 996–1003

  13. Nagaraju PV, Gupta AD (2006) Study of gate leakage current in symmetric double gate MOSFETs with high-j/stacked dielectrics. Thin Solid Films 504:317–320

    Article  CAS  Google Scholar 

  14. Mukhopadhyaya S, Kimb K, Kimb J-J, Lob S-H, Joshib RV, Chuangb C-T, Roy K (2007) Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectron J 38:931–941

    Article  Google Scholar 

  15. Chang L, Yang KJ, Yeo Y-C, Polishchuk I, Kin T-J, Hu C (2002) Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs. IEEE Trans Electron Devices 49(12):2288–2295

    Article  Google Scholar 

  16. Majkusiak B, Walczak J (2006) Simulation of the gate tunnel current in the double gate (DG) MOS transistor. J Comput Electron 5:143–148

    Article  CAS  Google Scholar 

  17. Vishvakarma SK, Komal Kumar V, Saxena AK, Dasgupta S (2011) Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET. Microelectron J 42:688–692

    Article  CAS  Google Scholar 

  18. Darbandy G, Ritzenthaler R, Lime F, Garduno I, Estrada M, Cerdeira A, Iniguez B (2011) Analytical modeling of direct tunneling current through gate stacks for the determination of suitable high-k dielectrics for nanoscale double-gate MOSFETs. Semicond Sci Technol 26:045002–045008

    Article  Google Scholar 

  19. Chaves F, Jiménez D, Suñé J (2012) Explicit model for the gate tunneling current in double-gate MOSFETs. Solid State Electron 68:93–97

    Article  CAS  Google Scholar 

  20. Darbandy G, Aghassi J, Sedlmeir J, Monga U, Garduño I, Cerdeira A, Iñiguez B (2013) Temperature dependent compact modeling of gate tunneling leakage current in double gate MOSFETs. Solid State Electron 81:124–129

    Article  CAS  Google Scholar 

  21. Sanjay, Prasad B, Vohra A (2020) Effect of interface dipole on channel engineering and on direct tunneling current in double gate MOSFET. Int J Num Model: Electronic Networks, Devices and Fields:e2754. https://doi.org/10.1002/jnm.2754

  22. Prasad SB and Vohra A(2020) “Metal gate electrode, channel and gate oxide engineering to improve DC and analog/RF performance of double-gate MOSFET for high-speed applications,” Appl Physics A, 126, pp. 400(1–10),

  23. Yadav R, Dutta AK (2022) A new charge-based analytical model for the gate current in GaN HEMTs. IEEE Trans Electron Dev 69(4):2210–2213

    Article  CAS  Google Scholar 

  24. Albahrani SA, Heuken L, Schwantuschke D, Gneiting T, Burghartz JN, Khandelwal S (2020) Consistent surface-potential-based modeling of drain and gate currents in AlGaN/GaN HEMTs. IEEE Trans Electron Dev 67(2):455–462

    Article  CAS  Google Scholar 

  25. Pradeep K, Poiroux T, Scheer P, Juge A, Ghibaudo G (2020) Modelling and analysis of gate leakage current and its wafer level variability in advanced FD-SOI MOSFETs,” Solid State Electronics 163, pp. 107643(1–6)

  26. Tyagi K, Verma A (2021) Modeling of the gate tunneling current in MFIS NCFETs. IEEE Trans Electron Devices 68(11):5886–5893

    Article  CAS  Google Scholar 

  27. Cerdeira A, Moldovan O, Iniguez B, Estrada M (2008) Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs. Solid State Electron 52:830–837

    Article  CAS  Google Scholar 

  28. Aditya M, Srinivasa Rao K (2022) Impact of high-K gate dielectric materials on uniformly doped dual gate FinFET for analog and digital applications. Silicon, Mar. https://doi.org/10.1007/s12633-022-01775-8

  29. Gowthaman N and Srivastava VM (2021) “Analysis of Nanometer-Scale n-Type Double-Gate (DG) MOSFETs Using High-ƙ Dielectrics for High-Speed Applications,” 44th International Spring Seminar on Electronics Technology (ISSE)

  30. Goel E (2022) Impact of high-K gate stack on subthreshold performance of double-gate (DG) MOSFETs. Silicon, Apr. https://doi.org/10.1007/s12633-022-01891-5

  31. Parija SK, Swain SK, Biswal SM, Adak S, Dutta P (2022) Performance analysis of gate stack DG-MOSFET for biosensor applications. Silicon. https://doi.org/10.1007/s12633-021-01622-2

  32. Tsormpatzoglou A, Dimitriadis CA, Clerc R, Quentin R, Pananakakis G, Ghibaudo G (2007) Semi-analytical modeling of Short-Channel effects in Si and Ge symmetrical double-gate MOSFETs. IEEE Transactions on Electron Devices 54(8):1943–1952

    Article  CAS  Google Scholar 

  33. Wong H-S P, Chan KK, and Taw Y (1997) “Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25 nm Thick Silicon Channel”. IEEE International Electron Device Meeting. IEDM Technical Digest. Washington, DC, USA, pp.427–430

  34. Basu D, Dutta AK (2006) An explicit surface-potentialbased MOSFET model incorporating the quantum mechanical effects. Solid State Electronics 50:1299–1309

    Article  CAS  Google Scholar 

  35. Ray B, Mahapatra S (2009) Modeling of channel potential and subthreshold slope of symmetric double-gate transistor. IEEE Trans Electron Dev 56(2):260–266

    Article  Google Scholar 

  36. Trivedi VP, Fossum JG (Aug. 2005) Quantum-mechanical effects on the threshold voltage of Undoped double-gate MOSFETs. IEEE Electron Device Lett 26(8):579–582

    Article  CAS  Google Scholar 

  37. Ghatak A, Lokanathan S (2004) Quantum mechanics: theory and application, 5th edition. McMillan, New Delhi

  38. Mondal I, Dutta AK (2008) An analytical gate tunneling current model for MOSFETs having ultrathin gate oxides. IEEE Trans Electron Dev 55:1682–1692

    Article  CAS  Google Scholar 

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Acknowledgements

We acknowledge the facility and support provided by the Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, India and the Department of Electronic Science, Kurukshetra University, Kurukshetra, India. We would also like to thank (Retd.) Prof. P. N. Ram, M J P Rohilkhand University, for his valuable inputs and interest in the work.

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Authors and Affiliations

  1. Electronics and Communication Engineering Department, Thapar Institute of Engineering and Technology, (formerly known as Thapar University) Patiala, Punjab, India

    Madhu Kushwaha, Arun Kumar Chatterjee, A. K. Chatterjee & Alpana Agarwal

  2. Department of Electronic Science, Kurukshetra University, Kurukshetra, Haryana, India

    B. Prasad

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  1. Madhu Kushwaha
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  2. Arun Kumar Chatterjee
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  3. B. Prasad
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  4. A. K. Chatterjee
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  5. Alpana Agarwal
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Correspondence to Madhu Kushwaha.

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Kushwaha, M., Chatterjee, A.K., Prasad, B. et al. A Generalized Analytical Approach to Model the Gate Tunneling Current in Nanoscale Double Gate MOSFETs. Silicon 14, 12513–12524 (2022). https://doi.org/10.1007/s12633-022-01943-w

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