Tri-Layer Lift-off Metallization Process Using Low Temperature Deposited SiN_x

Abstract

A tri-level resist scheme using low temperature (<50°C) deposited SiN_x ratfier than Ge for the transfer layer has been developed. This allows use of an optical stepper for lithographic patterning of the emitter-base junctions in GaAs/AlGaAs heterojunction bipolar transistors (HBTs) where a conventional lift-off process using a single level resist often leads to die presence of shorts between metallizations. The plasma-enhanced chemically vapor deposited (PECVD) SiN_x shows a sligtly larger degree of Si-H bonding compared to nitride deposited at higher temperature (275°C), and is under compressive stress (-5 x 10¹⁰ dyne · cm^-2) which is considerably relieved upor thermal cycling to 500°C (∼1.5 x 10¹⁰ dyne · cm^-2 after cool-down). This final stress is approximately a factor of two higher man conventional PECVD SiN_x cycled in the same manner. The adhesion of the low temperature nitride to die underlying polydimediylglutarimide (PMGI) base layer in the tri-level resist is excellent, leading to high yields in the lift-off metallization process. These layers are etched in Electron Cyclotron Resonance (ECR) discharges of SF₆ or O₂, respectively, using low additional dc bias (≤ — 100V) on the sample. Subsequent deposition of the HBT base metallization (Ti/Ag/Au) and lift-off of the tri-level resist produces contacts with excellent edge definition and an absence of shorts between metallization.