GERMANIUM (Ge) has exhibited advantages of higher carrier mobility and lower processing temperature compared with Si devices. These make Ge to be an alternative for applications of ultrascaled CMOS logic devices and thin-film transistors (TFTs) as top layer in three-dimensional integrated circuits [1,2,3]. In the past few years, great efforts have been focused on surface passivation, gate dielectric, and channel engineering for Ge p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs), which have contributed to significant improvement in electrical performance for the p-channel devices.

But for Ge n-channel MOSFETs, low effective carrier mobility (μeff) caused by poor interfacial layer of gate stack strongly limits the performance of the devices. Various surface passivation techniques including Si passivation [1], plasma post-oxidation [4], and InAlP passivation [5] and several high-κ dielectrics including HfO2, ZrO2 [6,7,8], Y2O3 [9], and La2O3 [10] have been explored in Ge nMOSFETs to boost the electron μeff. It was demonstrated that ZrO2 dielectric integrated with Ge channel can provide a robust interface due to that a GeO2 interfacial layer can react and intermix with the ZrO2 layer [7]. A decent hole μeff has been reported in Ge p-channel transistors [6,7,8], while there is still a lot of room for improvement in electron μeff for their counterparts.

In this work, Ge nMOSFETs with ZrO2 gate dielectric are fabricated to achieve improved μeff over Si in the entire range of inversion charge density (Qinv). Ge transistors obtain a 50% improvement in electron μeff compared to the Si universal mobility at a medium Qinv of 5.0 × 1012 cm−2.


The key process steps for fabricating Ge nMOSFETs on 4-inch p-Ge(001) wafers with a resistivity of 0.136–0.182 Ω cm are shown in Fig. 1a. The source/drain (S/D) regions were implanted with phosphorous ion at a dose of 1 × 1015 cm−2 and an energy of 30 keV followed by dopant activation annealing at 600 °C. After the pre-gate cleaning, Ge wafers were loaded into an atomic layer deposition chamber for the formation of the gate dielectric layer(s): Al2O3/O3 oxidation/ZrO2, ZrO2, or O3 oxidation/ZrO2 for wafers A, B, or C, respectively. For wafer A, 0.9 nm Al2O3 was used to protect the channel surface during O3 oxidation. O3 oxidation was carried out at 300 °C for 15 min for both wafers A and C. For all the wafers, the thickness of ZrO2 was ~ 3.3 nm. Subsequently, TiN(100 nm) gate metal was deposited via physical reactive sputtering, and lithography patterning and reactive ion etching were used to form the gate electrode. After that, a 25-nm-thick Ni layer was deposited in S/D regions. Finally, the post-metallization annealing (PMA) at 350 °C for 30 s was carried out to form the Ni germanide and improve the interface quality. Schematic and microscope images of the fabricated transistor are shown in Fig. 1b, c, respectively.

Fig. 1
figure 1

a Key process steps for fabricating Ge nMOSFETs. b Cross-sectional schematic and c microscope image of the fabricated devices

Figure 2a, b shows the high-resolution transmission electron microscope (HRTEM) images of the gate stacks on wafers A and B, respectively. The unified thickness of the Al2O3/GeOx interfacial layer (IL) for wafer A is ~ 1.2 nm indicating the 0.2–0.3 nm GeOx. For the device on wafer B, an ultrathin GeOx IL was experimentally demonstrated [7].

Fig. 2
figure 2

HRTEM images of a TiN//ZrO2/Al2O3/GeOx/Ge, b TiN/ ZrO2/GeOx/Ge stacks for the devices on wafers A and B, respectively

Results and Discussion

The measured capacitance (C) and the leakage current (J) characteristics for Ge MOS capacitors on wafers A, B, and C are measured and shown in Fig. 3a, b, respectively. The equivalent oxide thickness (EOT) of the devices on wafers A, B, and C is extracted to be 1.79, 0.59, and 0.83 nm, respectively. Assuming the GeOx IL provides an extra EOT of ~ 0.25 nm for wafers A and C by comparing wafers B and C, the 3.3 nm ZrO2 contributes an EOT of ~ 0.6 nm with κ value of ~ 21.8, which is consistent with the previous reported value of amorphous ZrO2 [11].These derived results also confirm that the thickness in GeOx IL on wafer B is negligible.

Fig. 3
figure 3

a Measured C as a function of voltage V characteristics for Ge pMOS capacitors on wafers A, B, and C. b J versus V curves for the devices. c Benchmarking of J (extracted at VFB ± 1 V) of the Ge MOS capacitors in this work against data obtained for similar bias conditions from the literature

The GeOx/Al2O3 IL for wafer A and GeOx IL for wafer C produces the EOT of ~ 1.2 and ~ 0.25 nm, respectively. The EOT of the devices can be further reduced by decreasing the IL thickness or improving the interface quality, and enhancing the permittivity of ZrO2 with some surface passivation, e.g., NH3/H2 plasma treatment [6]. Figure 3c compares J versus EOT characteristics for the Ge nMOSFETs in this work against values for other reported Ge devices [5, 12,13,14,15,16,17]. It is also observed that the results are consistent with the reported Ge MOS with ultra-thin EOT following the same trends, indicating the difference of leakage current shown in Fig. 3b should be mainly attributable to the difference of EOT.

Figure 4a shows measured drain current (ID) and source current (IS) versus gate voltage (VG) curves of Ge nMOSFETs from wafers A, B, and C. All transistors have a gate length LG of 4 μm and a gate width W of 100 μm. The point subthreshold swing (SS), defined as dVG/d(logID), as a function of ID curves for the transistors in Fig. 4a is calculated and shown in Fig. 4b. It is clarified that the transistor on wafer A exhibits the degraded ID leakage floor and SS compared to the devices on wafers B and C. Besides the increase in EOT in devices on wafer A would bring in the increment of SS, these phenomenon should be partly attributed to the fact that the device with the Al2O3 inserted layer has a higher density of interface traps (Dit) within the bandgap of the Ge channel in comparison with the wafers B and C.

Fig. 4
figure 4

a Measured ID and IS versus VGS curves of Ge nMOSFETs on wafers A, B, and C. b Point SS as a function of ID for the transistors. c IDVD characteristics show that the Ge nMOSFET on wafer A has a higher drive current compared to the devices on wafers B and C

Figure 4c shows the measured output characteristics, i.e., IDVD curves for various values of gate overdrive |VGVTH| of the devices demonstrating that the Ge transistor on wafer A achieves significantly improved drive current compared to the devices on wafers B and C. Here, VTH is defined as VGS corresponding to an ID of 10−7 A/μm. Considering the identical conditions for S/D formation, the boosted IDS for transistors on wafer A indicates the higher μeff [18,19,20,21]. The Al2O3 layer has not led to the degradation of Dit performance near the conduction band of the Ge channel.

Figure 5a shows the total resistance Rtot as a function of LG for the Ge nMOSFETs with ZrO2 dielectric with an LG ranging from 2 to 10 µm. The values of Rtot are extracted at a gate overdrive of 0. 6 V and a VD of 0.05 V. The S/D resistance RSD of the transistors is extracted to be ~ 13.5 kΩ μm, utilizing the fitted lines intersecting at the y-axis. The similar RSD is consistent with the identical process of PMA and S/D formation. The channel resistance RCH values of the devices are obtained by the slope of the fitted lines, i.e., ΔRtotLG, which can be used for calculating the μeff characteristics of Ge nMOSFETs. To evaluate the interface quality, interface trap densities (Dit) were extracted by the following equation according to Hill’s method [17]:

$$D_{{{\text{it}}}} = \frac{{2G_{{{\text{m}}\max }} /\omega }}{{qA\left[ {\left( {\frac{{G_{{{\text{mmax}}}} }}{{\omega C_{{{\text{ox}}}} }}} \right) + \left( {1 - C_{{\text{m}}} /C_{{{\text{ox}}}} } \right)^{2} } \right]}}$$

where q is the electronic charge, A is the area of the capacitor, Gm,max is the maximum value of measured conductance, with its corresponding capacitance Cm, ω is the angular frequency, and Cox is gate oxide capacitance. The Dit values are calculated to be 3.7, 3.2, and 2.3 × 1012 eV−1 cm−2 for the devices on wafers A, B, and C, respectively.

It is known that the calculated values correspond to the midgap Dit. The device with Al2O3 IL on wafer A has a higher midgap Dit compared to the devices on wafers B and C. This is consistent with the results in Figs. 3a and 4a, and the higher midgap Dit gives rise to a larger depletion capacitance dispersion in wafer A causing a higher leakage current of IDS in comparison with the other two wafers. Note the wafer A should have the lower Dit near the conduction bandgap due to its higher μeff over wafers B and C.

Fig. 5
figure 5

a Rtot versus LG curves for Ge nMOSFETs on wafers A, B, and C. The fitted line intersecting at the y-axis and the slope of linear fit lines are utilized to extract the RSD and RCH, respectively. b μeff for the Ge nMOSFETs in this work versus previously published results for unstrained Ge transistors. The devices on wafer A show the improved μeff than the Si universal mobility in the entire range of Qinv

It is well known that μeff is the bottleneck for high drive current and transconductance in Ge nMOSFETs. Here, μeff can be calculated by \(\mu_{{{\text{eff}}}} = 1/[WQ_{{{\text{inv}}}} (\Delta R_{{{\text{tot}}}} /\Delta L_{{\text{G}}} )]\), where ΔRtotLG is the slope of the Rtot versus LG as shown in Fig. 5a. Qinv can be obtained by integrating the measured CinvVG curves. In Fig. 5b, we compare the μeff versus Qinv of the Ge nMOSFETs on wafers A, B, and C with those reported previously in [18, 22,23,24,25]. The extracted peak μeff values of the transistors on wafers A and C are 795 and 682 cm2/V s, respectively, and that of Ge nMOSFETs on wafer B is 433 cm2/V s. Ge nMOSFETs with Al2O3 IL achieve a significantly improved μeff in comparison with the transistors on wafer B or C, the devices in [18, 22,23,24,25] in a high field, and Si universal mobility in the entire Qinv range. At a Qinv of 5 × 1012 cm−2, a 50% μeff enhancement is achieved in devices on wafer A as compared to the Si universal mobility. This demonstrates that by protecting the channel surface for preventing the intermixing of ZrO2 and GeOx using Al2O3, a high-quality interface between gate insulator and Ge is realized to boost the mobility characteristics, which is also reported in the previous studies of Ge MOSFETs with ultrathin EOT [26]. μeff in transistors on wafer C is higher than the Si universal at a Qinv of 2.5 × 1012 cm−2, although it rapidly decays with the increase in Qinv range. This indicates that the used O3 oxidation before ZrO2 deposition would improve the interfacial quality to some extent; however, it does not lead to enough flat channel surface to effectively suppress the surface roughness scattering of the carrier at high Qinv due to the intermixing of ZrO2 and GeOx, since it is reported that the generation of oxygen vacancies during the intermixing would increase the short-range order (SRO) roughness [27]. Optimizing the O3 oxidation process or reducing the Al2O3 IL thickness can make the Ge transistor achieve a reduced EOT while maintaining a higher μeff at the high Qinv.


The impacts of gate dielectric structure and morphology on Ge nMOSFET electrical characteristics are investigated. An Al2O3/ZrO2 gate dielectric provides for significantly-improved μeff as compared to the Si universal mobility. μeff can be improved by inserting an Al2O3 layer between the ZrO2 and Ge channel, which, however, inevitably leads to a larger EOT. Al2O3-free Ge nMOSFETs with O3 oxidation of the Ge surface prior to ZrO2 deposition achieve a peak μeff of 682 cm2/V s which is higher than that of Si at the similar Qinv.