Performance Evaluation of Inversion Mode and Junctionless Dual-Material Double-Surrounding Gate Si Nanotube MOSFET for 5-nm Gate Length

Abstract

In this work, drain current I_D for 5-nm gate length with dual-material (DM) double-surrounding gate (DSG) inversion mode (IM) and junctionless (JL) silicon nanotube (SiNT) MOSFET have been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. For this work, we used the non-equilibrium Green’s function (NEGF) approach and self-consistent solution of Poisson’s equation with Schrödinger's equation. The conduction band splitting into multiple sub-bands has been considered and there is no doping in channel in case of IM SiNT MOSFET. The effect of DM gate engineering for SiNT channel radius 1.5 nm with 0.8-nm gate oxide (SiO₂) thickness on I_D has been studied. A comparison of results has been done between IM DM DSG and JL DM DSG SiNT. In case of JL, doping concentration is optimized for two concerns: (i) to get the same I_On current as IM device and (ii) to get the same threshold voltage V_Th as IM. This has resulted in 10² and 10³ times smaller I_Off in matching I_On and V_Th optimized device, respectively, as compared to IM. It is found that DM gate engineering reduces drain-induced barrier lowering (DIBL) for both IM and JL SiNT MOSFET. In this work, JL have much smaller DIBL ~15 mV/V, almost an ideal SS ~60 mV/dec, and higher I_On/I_Off ratio ~2.18 × 10⁸ as compared to available CGAA literature results.