1 INTRODUCTION

The use of monolithic integrated circuits in the microwave frequency range (microwave MICs) plays an important role in improving the technical characteristics of electronic devices and makes it possible to reduce significantly the mass and volume of equipment, as well as the labor intensity and cost of manufacturing them [1, 2]. The elements library is one of the most important components in the design of microwave MICs [3]. Their construction requires a comprehensive study of the static and frequency properties of test structures (discrete transistors, passive components), which makes it possible to obtain parametric scalable models. Increasing the accuracy of creating models of these components hugely simplifies the development of subsequent hierarchical systems based on them.

AWR DESIGN ENVIRONMENT (AWRDE) by Cadence Design System is one of the leading software products used for the design and development of RF and microwave devices. It uses a single object-oriented data model that synchronizes the work on a project without using compilers. For designing circuits, a built-in extensive library of schematic elements is provided. However, the existing models require clarification related to the features of the devices’ manufacturing technological process and their topological parameters. Therefore, the technological center developing solid-state devices in the microwave frequency range must have its own precise models of active and passive components, which are the base of the norms and rules for designing complex integrated circuits.

In this paper, we study high electron mobility transistors based on AlGaAs/InGaAs/GaAs pHEMT heterostructures with a T-shaped electron lithographic gate 150 nm long and thinned plate thickness of 100 μm, fabricated according to the NRNU MEPhI technological process by analyzing its static and frequency properties in the frequency range up to 50 GHz. A detailed description of the technological process of manufacturing experimental samples and topology of devices is presented in [4]. The aim of this study is to improve the accuracy of models of active elements created in the framework of the development of a MIC of a low-noise amplifier, mentioned in [4], by refining the nonlinear gate-channel capacitance dependences on the supply and bias voltages, as well as the IV characteristics of the model.

2 EXPERIMENTAL RESULTS

The IV characteristics were measured on a Cascade Microtech PM8 manual probe station with a pulsed power supply AMCAD PIV SYSTEM (PS) in the frequency range 0.1–50 GHz. The measuring filter bandwidth (1 kHz) made it possible to ensure the sufficient uniformity of the frequency response of the device for signal transmission with almost no distortion of its form. The input signal power (–20 dBm) was chosen to reduce the impact of the emerging noise effects.

Figure 1 shows the IV and frequency characteristics of an experimental sample of an AlGaAs/InGaAs/GaAs transistor with four gate sections 50 μm wide. The S-parameters were measured in the frequency range from 5 to 45 GHz. The range limitation was due to the Bias Tee used. It is shown that the transistor has an initial drain current of more than Id = 250 mA/mm and transconductance of more than 250 mS/mm (Fig. 1a), as well as a voltage gain of more than 12 dB in the X frequency range (Fig. 1d). The scatter of the values of the measured S-parameters depending on the location of the measured sample on the plate is ±1.8 dB.

Fig. 1.
figure 1

Characteristics of the experimental sample: drain characteristics at Ugs ranging from –0.3 to 1 V (a), gate characteristics at Uds = 0 V (b); S-parameters measured at Ugs = –0.3 V and Uds = 3.2 V in the frequency range from 5 to 45 GHz (c–f). Solid lines represent typical experimental results, small dots on the results of S-parameters mark the boundaries of the range of experimental data obtained in various areas of plate, dashed lines show the computed values.

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3 EXTRACTION OF THE EXTRINSIC AND INTRINSIC PARAMETERS OF TRANSISTORS

The method of extracting the extrinsic and intrinsic parameters of a transistor is analogous to that proposed in [5]. The schematics used for the extraction of the extrinsic and intrinsic parameters of transistor are presented in Fig. 2. At the same time, for the extraction of the extrinsic parameters of a transistor, an alternative scheme to the Open-Short method [6], which makes it possible to extract the parameters without changing its configuration and reducing the labor cost of the experimental studies, was used (Fig. 2a). The use of the AWR Design Environment software makes it possible to perform calculations in the open and closed states of the transistor channel without changing the configuration of the circuit.

Fig. 2.
figure 2

Principled schematics for the extraction transistor parameters: (a) for extrinsic parameters (the area marked with a square simulates the transistor channel); (b) for the intrinsic parameters.

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Figure 3 shows the theoretically calculated frequency dependence of the transistor’s off-state conductivity. The observed resonances at frequencies of 28.5 and 45 GHz are associated with the presence of LC and RC sections in the circuit. In particular, the channel capacitance (C4 and C5 in Fig. 2a) affects both resonances, while the inductances of the gate (L1) and drain (L2) regions affects the magnitude and position of the resonances mainly at higher frequencies. The capacitance of the gate region (C3) has almost no impact on the characteristics of the considered peaks, while the capacitances of the gate-pad (C1) and drain-pad (C2) regions only have a significant effect on the position of the peaks and an insignificant effect on their magnitude. The error does not exceed 4% in the entire studied frequency range.

Fig. 3.
figure 3

Theoretically calculated frequency responses of transistor conductivity in the off-state channel: (a) real part; (b) imaginary part.

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The intrinsic parameters of the transistor were determined by solving the following equation [7]:

$$\left[ {\begin{array}{*{20}{c}} {{{i}_{{gs}}}} \\ {{{i}_{{ds}}}} \end{array}} \right] = \left[ {\underbrace {\begin{array}{*{20}{c}} {{{Y}_{{gs}}} + {{Y}_{{gd}}}}&{{{Y}_{{gd}}}} \\ {{{g}_{m}} + j\omega {{C}_{m}}~ - ~{{Y}_{{gd}}}}&{{{Y}_{{ds}}} + ~{{Y}_{{gd}}})} \end{array}}_{{{Y}_{{int}}}}} \right]\left[ {\begin{array}{*{20}{c}} {{{v}_{{gs}}}} \\ {{{v}_{{ds}}}} \end{array}} \right],$$
(1)

where

$${{Y}_{{gs}}} = ~\frac{{j\omega {{C}_{{gs}}}}}{{1 + j\omega {{C}_{{gs}}}{{R}_{i}}}},$$
(2)
$${{Y}_{{gd}}} = ~\frac{{j\omega {{C}_{{gd}}}}}{{1 + j\omega {{C}_{{gd}}}{{R}_{j}}}},$$
(3)
$${{Y}_{{ds}}} = j\omega {{C}_{{ds}}} + {{g}_{{ds}}}.$$
(4)

The expression for the intrinsic admittance was obtained by substituting expressions (2), (3), and (4) into (1):

$${{Y}_{{int}}} = \left[ {\begin{array}{*{20}{c}} {j\omega ({{C}_{{gs}}} + {{C}_{{gd}}})}&{ - j\omega {{C}_{{gd}}}} \\ {{{g}_{m}} + j\omega ({{C}_{m}}~ - ~{{C}_{{gd}}})}&{{{g}_{{ds}}} + j\omega ({{C}_{{gs}}} + {{C}_{{gd}}})} \end{array}} \right].$$
(5)

4 THE DEVELOPMENT OF THE NONLINEAR MODEL

During the development of the nonlinear model, various transistor models used in commercial CADs, including the Angelov model [8], Curtice quadratic and cubic models [9, 10], Chalmers model [11], modified Materka model [12], and Yhland model [13], were studied. Based on the results of preliminary studies, it was found that the Chalmers model had the highest convergence in our case; hence, it was chosen for the design of the nonlinear model of the considered pHEMT (Fig. 4).

Fig. 4.
figure 4

Principled schematics for the design of a nonlinear pHEMT model.

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In the calculations, not only the nonlinear current sources but also the parameters of the nonlinear gate-source and drain-gate capacitances depending on the supply and bias voltages were considered. In Fig. 4 these parameters are set as “1” and “2”, respectively. At the same time, the drain-source capacitance is not considered as a nonlinear element because it has a relatively weak dependence on the supply and bias voltages [14].

The dependence of the drain current on the supply voltage and bias voltage was defined as follows:

$${{I}_{d}} = {{I}_{{pk}}}\left( {1 + \tanh \left( {{\Psi }} \right)} \right)\left( {1 + \lambda {{V}_{{ds}}}} \right){\text{tanh}}\left( {\alpha {{V}_{{ds}}}} \right),$$
(6)
$${\text{where }\Psi } = {{P}_{{1m}}}\left( {{{V}_{{gs}}} - {{V}_{{pk}}}} \right) + \mathop \sum \limits_{i = 2}^6 {{P}_{i}}{{\left( {{{V}_{{gs}}} - {{V}_{{pk}}}} \right)}^{i}},$$
(7)
$$\alpha = {{\alpha }_{R}} + {{\alpha }_{S}}\left( {1 + \tanh \left( {{\Psi }} \right)} \right),$$
(8)
$${{P}_{{1m}}} = {{P}_{1}}\left( {1 + {{B}_{1}}{\text{/}}{\kern 1pt} {{{\cosh }}^{2}}\left( {{{B}_{2}}{{V}_{{ds}}}} \right)} \right),$$
(9)
$${{V}_{{pk}}} = {{V}_{{pk0}}} + ({{V}_{{pks}}} - {{V}_{{pk0}}}){\text{tanh}}\left( {{{\alpha }_{S}}{{V}_{{ds}}}} \right).$$
(10)

The dependence of the drain current of the transistor was obtained taking the breakdown voltage based on expressions (6)–(10) into consideration:

$$\begin{gathered} {{I}_{d}} = {{I}_{{pk}}}\left( {1 + \tanh \left( {{\Psi }} \right)} \right)\left( {1 + \lambda {\text{*}}{{V}_{{ds}}}} \right){\text{tanh}}\left( {\alpha {{V}_{{ds}}}} \right) \\ \times \,\,\left( {1 + \lambda {{V}_{{ds}}} + {{\lambda }_{{SB}}}{{e}^{{{{V}_{{dg}}} - {{V}_{{TR}}}}}}} \right), \\ \end{gathered} $$
(11)

where Vpk = Vpk0 + (Vpks – Vpk0)tanh(αSVds) – VSB2(Vdg – VTR)2.

In the analysis of the gate current, the maximum possible saturation current density Igss, the gate-source bias voltage Ugs, the threshold voltage Uth, and the nonideality parameter were considered:

$${{I}_{g}} = {{I}_{{gss}}}\left( {\exp \left( {q\frac{{{{V}_{{gs}}} - {{V}_{{th}}}}}{{{{N}_{{gs}}}kT}}} \right) - 1} \right),$$
(12)

where q is the electron charge, k is the Boltzmann constant, and T is the ambient temperature.

The calculated values of the coefficients obtained by the analysis of expressions (6)–(12) are presented in Table 1.

Table 1.   Current source parameters
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In Fig. 1, the dashed curves present the transistor’s theoretically computed IV characteristics and frequency responses obtained after using the expressions given above and coefficients from Table 1. The results make it possible to characterize base transistors adequately. The slight deviations observed of the theoretical curves from the experimental values on the IV characteristics and S22 does not exceed 3%. The error of the model may be associated with the additional reactive components in the transistor’s output circuit and with the impact of the “kink-effect” in the low drain voltage region on the current of the device.

Using the obtained data in the given ranges of the drain current and drain-source voltage, the frequency response characteristics of Mason’s unilateral gain, the modulus of the current transfer coefficient |h21|, and maximum available/stable voltage gain were computed and shown in Fig. 5.

Fig. 5.
figure 5

Frequency responses of Mason’s gain ratio (curve 1), the modulus of the current transfer coefficient (curve 2) and the maximum available/stable gain (MAG/MSG) (curve 3). Markers represent experimental data of the typical characteristic, dashed lines show computed values.

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The limiting frequencies of the current gain and power gain were determined by the standard extrapolation of the frequency dependences of |h21| and Mason’s gain ratio to higher frequencies. It is shown that for the considered transistor these values were ft = 75 GHz and fmax = 103 GHz, respectively. At the same time, the maximum available power gain was 17 dB at a frequency of 10 GHz.

5 CONCLUSIONS

The designed nonlinear model of a pseudomorphic 0.15 μm pHEMT AlGaAs/InGaAs/GaAs transistor made it possible to characterize the device in the drain voltage range up to 6 V and its transfer characteristic in the frequency range 5–45 GHz. The parametrization of the transistor was carried out based on a refined Chalmers model. It is shown that the proposed model makes it possible to describe the IV characteristics of the studied device adequately in the range of drain currents from 0 to 100 mA and the frequency range from 5 to 45 GHz. The error of the model does not exceed 3%. The considered range of currents and voltages is the operating range for the selected transistor; therefore, the results attained can be used to construct an elements library of active components in the microwave frequency range based on the using pseudomorphic heterostructures of AIIIBV compounds.