Skip to main content
SpringerLink
Log in

Parallel-Pipeline Processing of Video Information in Multiprocessing Heterogeneous Systems on a Chip

  • Published:
Russian Microelectronics Aims and scope Submit manuscript

Abstract

Moving from homogeneous to heterogeneous architectures offers performance, size, weight, and power advantages, which are especially important for embedded solutions. However, the development of parallel software for heterogeneous computing systems is a rather difficult task due to the requirements of high performance, easy programmability, and scalability. The paper investigates the efficiency of parallel-pipeline processing of video information in multicore heterogeneous systems on a chip (SoC). A mathematical model of the used structures is described and the criteria for efficiently processing video data are formulated, based on which the target function is built. The typical scheme for parallel-pipeline processing of video data using various streaming video processing accelerators (DSP, GPU, ISP, VDP, VPU, etc.) is presented. A scheme for parallel-pipeline processing of video data on a heterogeneous 1892VM248 SoC is developed. A technique for efficient parallel-pipeline video information processing in heterogeneous computing SoCs, including a software stack consisting of an operating system level, a programming technology level, and an application level, is proposed. A comparative analysis of the most common programming technologies for heterogeneous SoCs, such as OpenCL, OpenMP, MPI, and OpenAMP, is carried out. The results of the analysis show that, depending on the purpose of the end device, two programming paradigms should be used: based on OpenCL technology (for embedded systems) and MPI technology (for intercore and interprocessor interactions). The results of parallel-pipeline processing in the face recognition problem confirms the effectiveness of the chosen solutions.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.

Similar content being viewed by others

REFERENCES

  1. Belyaev, A.A., Gavrilov, S.V., Kuznetsov, D.A., et al., Evolution of multi-core heterogeneous computing systems in the field of video data processing, in Tr. V Vseros. nauch.-tekhn. konf. Problemy razrabotki perspektivnykh mikro- i nanoelektronnykh sistem – 2014 (Proceedings of the 5th All-Russia Conference on Problems of Developing Promising Micro- and Nanoelectronic Systems MES-2014), Stempkovskii, A.L., Ed., Moscow: IPPM RAN, 2014, part 4, pp. 129–134.

  2. Laude, T., Adhisantoso, Y.G., Voges, J., et al., Comprehensive video codec comparison, APSIPA Trans. Signal Inform. Process., 2019, vol. 8, p. e30. https://doi.org/10.1017/ATSIP.2019.23

    Article  Google Scholar 

  3. ELVIS. https://multicore.ru. Accessed July 19, 2020.

  4. Buffer Sharing and Synchronization. www.kernel.org/ doc/html/v4.16/driver-api/dma-buf.html. Accessed July 19, 2020.

  5. OpenMP. https://www.openmp.org/. Accessed July 19, 2020.

  6. MPI. https://computing.llnl.gov/tutorials/mpi/. Accessed July 19, 2020.

  7. OpenCL. https://www.khronos.org/opencl/. Accessed July 19, 2020.

  8. OpenAMP. https://www.openampproject.org/. Accessed July 19, 2020.

  9. Yanakova, E.S., Macharadze, G.T., Kostulin, N.V., and Tyurin, A.A., Solving large SLE on heterogeneous SOC of ‘multicore’ series, Probl. Razrab. Persp. Mikro- Nanoelektron. Sist., 2020, no. 1, pp. 70–75. https://doi.org/10.31114/2078-7707-2020-1-70-75

  10. FaceScrub Database. http://megaface.cs.washington.edu/ results/facescrub.html. Accessed July 19, 2020.

  11. Intel Xeon Gold 6140 Processor. https://www.intel.in/ content/www/in/en/products/processors/xeon/scalable/ gold-processors/gold-6140.html. Accessed July 19, 2020.

Download references

Author information

Authors and Affiliations

  1. National Research University, Moscow Institute of Electronic Technology (MIET), Moscow, Russia

    E. S. Yanakova & L. G. Gagarina

  2. National Research University, Moscow Power Engineering Institute (MPEI), Moscow, Russia

    G. T. Macharadze

  3. AO NPC ELVEES, Moscow, Russia

    G. T. Macharadze & A. A. Shvachko

Authors
  1. E. S. Yanakova
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. G. T. Macharadze
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. L. G. Gagarina
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. A. A. Shvachko
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to L. G. Gagarina.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yanakova, E.S., Macharadze, G.T., Gagarina, L.G. et al. Parallel-Pipeline Processing of Video Information in Multiprocessing Heterogeneous Systems on a Chip. Russ Microelectron 51, 619–626 (2022). https://doi.org/10.1134/S1063739722070113

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1134/S1063739722070113

Keywords:

Search

Navigation