Abstract
The problems of logic and timing analysis, arising in the design and optimization stages of complex functional VLSI units, are considered. The new method of logic and timing simulation of CMOS circuits from interval estimates, which ensure the integration of two contrary approaches to solving the problem of the performance analysis, namely, the analysis of critical paths and simulation of test sequences, is proposed. The selection of the interval approach is determined by the substantial increase in specific weights of parameter variations of nanometer elements in the timing calculations.
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Original Russian Text © S.V. Gavrilov, O.N. Gudkova, A.L. Stempkovskiy, 2012, published in Izvestiya Vysshikh Uchebnykh Zavedenii. Elektronika, 2012, No. 4, pp. 40–49.
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Gavrilov, S.V., Gudkova, O.N. & Stempkovskiy, A.L. The analysis of the performance of nanometer intellectual property blocks based on interval simulation. Russ Microelectron 42, 396–402 (2013). https://doi.org/10.1134/S1063739713070068
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DOI: https://doi.org/10.1134/S1063739713070068