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Timing Closure for Multi-Million-Gate Integrated Circuits

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Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 166))

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Abstract

Sophisticated integrated circuits (ICs) can be classified as processors (CPUs), application-specific integrated circuits (ASICs) or systems-on-a-chip (SoCs), which embed CPUs and intellectual property blocks into ASICs. Mass-produced on silicon chips, these circuits fuel consumer and industrial electronics, maintain national and international computer networks, coordinate transportation and power grids, and ensure the competitiveness of military systems. The design of new integrated circuits requires sophisticated optimization algorithms, software and methodologies—collectively called Electronic Design Automation (EDA)—which leverage synergies between Computer Science, Computer Engineering and Electrical Engineering.

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Notes

  1. 1.

    This is in contrast to timing-driven placement, which in previous literature usually refers to the application of net weights during placement that are based on timing information. Here we are referring to the detailed placement of a small number of gates while interacting incrementally with a timing analysis engine.

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Papa, D.A., Markov, I.L. (2013). Timing Closure for Multi-Million-Gate Integrated Circuits. In: Multi-Objective Optimization in Physical Synthesis of Integrated Circuits. Lecture Notes in Electrical Engineering, vol 166. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1356-1_1

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  • DOI: https://doi.org/10.1007/978-1-4614-1356-1_1

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  • Publisher Name: Springer, New York, NY

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