Abstract
An ICP-AES procedure for analyzing high-purity silicon, which is implemented on up-to-date standard equipment and intended to determine 44 impurities with detection limits of n × 10−8−n × 10−6 wt % in silicon, is described. The procedure is compared with ICP-AES procedures, conforming to GOST (State Standard) and published in the literature, in quantity of determined impurities and their detection limits.
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Original Russian Text © A.V. Shaverina, A.R. Tsygankova, I.R. Shelpakova, A.I. Saprykin, 2012, published in Zavodskaya Laboratoriya. Diagnostika Materialov, 2012, Vol. 78, No. 4, pp. 9–13.
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Shaverina, A.V., Tsygankova, A.R., Shelpakova, I.R. et al. ICP-AES analysis of high-purity silicon. Inorg Mater 49, 1283–1287 (2013). https://doi.org/10.1134/S0020168513140082
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DOI: https://doi.org/10.1134/S0020168513140082