Abstract
We explore the energy dissipation of the Linear Processor Array (LPA) as a function of the number of available resources (Processor Units P) within the array. This number P is an important parameter, as it reflects performance, relates parallel processing to energy dissipation, and influences the scaling of the various parts of the LPA architecture (memory, address generator, communication network).
To make a comparison of the different design variants for a fixed datawidth possible, we propose a high-level energy dissipation model of the processor, which is based on a detailed analysis of a general convolution algorithm.
It is shown that the energy dissipation of the LPA can roughly be described by the relationship E total ∼ N/P with N presenting the datawidth in pixels. This relationship is derived from two observations: first, the largest contribution to E total is formed by the energy dissipated by the memories, and second, in our model of the LPA, the datawidth of the memories corresponds with the number of pixels N to be processed, which results in an increase of the access rate when P decreases.
Furthermore, we have shown that the energy dissipation caused by communication within the LPA, increases with increasing number of resources: the trade-off between communication versus computation in parallel computing. This turns out to be negligible in the total energy dissipation, and we therefore conclude, that the optimum solution is found, when a full number of resources is applied within the LPA.
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References
R.P. Kleihorst et al., “A Low Power High-Performance Smart Camera Processor,” in ISCAS, Sydney, 2001.
J.Y.F. Hsieh and T.H.Y. Meng, “Low-Power DV Encoder Architecture for Digital CMOS Camcorder,” in ICASSP. Phoenix, Arizona, 1999.
N. Ranganathan, N. Vijaykrishhnan, and N. Bhavanishankar, “A Linear Array Processor with Dynamic Frequency Clocking for Image Processing Applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 4, 1998, pp. 435-445.
C. Jansson, P. Ingelhag, C. Svensson, and R. Forchheimer, “An Addressable 256 × 256 Photodiode Image Sensor Array with an 8-Bit Digital Output,” in Kluwer Academic Publisher, Boston, vol. 4. 1993, pp. 37-49.
K. Chen, M. Afghahi, P. Danielsson, and C. Svensson, “PASIC: A Processor-A/D Converter-Sensor Integrated Circuit,” IEEE, 1990, pp. 1705-1708.
P.P. Jonker, “Why Linear Arrays Are Better Image Processors,” IEEE Computer Society Press. Proc. 12th IAPR Int. Conf. on Pattern Recognition, Conf. D: Parallel Computing (ICPR12), Jerusalem, Israel, Oct. 9–13, 1994, vol. III, pp. 334-338.
A. der Avoird, R.P. Kleihorst et al., “XeTaL Design Vehicle,” Technical report, Philips Natlab, 1998.
R. Manniesing, “Power Analysis of a Linear Processor Array, Related to Low-Level Image Algorithms,” Master's thesis, Delft University of Technology, Electrical Engineering, 1999.
J.M. Rabaey and M. Pedram (Eds.), Low Power Design Methodologies. Boston: Kluwer Academics Publishers, 1996, ISBN 0-7923-9630-8.
J.C. Gealow and C.G. Sodini, “A Pixel-Parallel Image Processor Using Logic Pitch-Matched to Dynamic Memory,” IEEE Journal of Solid-State Circuits, vol. 34, 1999.
E.R. Komen, “Low-Level Image Processing Architectures, Compared for Some Non-Linear Recursive Neighborhood Operations,” Ph.D. Thesis, TU Delft 1990.
K.R. Castleman, Digital Image Processing. London: Prentice Hall International (UK) Limited, 1996, ISBN 0-13-398058-8.
S.Y. Kung, “VLSI Array Processors,” IEEE ASSP, 1985, pp. 4-22.
S.A. Ward and R.H. Halstead, Computation Structures. Cambridge, Massachusetts Londen, The MIT Press, 1990, ISBN 0-26223139-5.
A.P. Chandrakasan and R.W. Brodersen, Low Power Digital CMOS Design. Boston: Kluwer Academics Publishers, 1995, ISBN 0-7923-9576-X.
J. Meerbergen, P.E.R. Lippens, W.F.J. Verhaegh, and A. de Werf, “Phideo: High-Level Synthesis for High-Throughput Applications,” Journal of VLSI Signal Processing 9, 1995, pp. 89-104.
R.P. Llopis and K. Goossens, “The Petrol Approach to High-Level Power Estimation,” in International Symposium on Low Power Electronics and Design. Monterey, CA, 1998, pp. 130-132.
R.P. Llopis, “A New Approach in High-Level Power Estimation,” in Design Automation and Test. Paris, France, 1998, pp. 31-35.
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Manniesing, R., Kleihorst, R., van der Avoird, A. et al. Power Analysis of a General Convolution Algorithm Mapped on a Linear Processor Array. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 37, 5–19 (2004). https://doi.org/10.1023/B:VLSI.0000017000.91377.a7
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DOI: https://doi.org/10.1023/B:VLSI.0000017000.91377.a7