Abstract
In this paper, a new Design for Testability (DFT) scheme is proposed, for the testing of LC-tank CMOS Voltage Controlled Oscillators (VCOs). The proposed test-circuit is capable of detecting hard (catastrophic) and soft (parametric) faults, injected in the VCO. The test result is provided by a digital Fail/Pass signal. Simulation results reveal the effectiveness of the proposed circuit. The overall silicon area requirement of the proposed DFT scheme is negligible.
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Dermentzoglou, L., Tsiatouhas, Y. & Arapoyanni, A. A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. Journal of Electronic Testing 20, 133–142 (2004). https://doi.org/10.1023/B:JETT.0000023677.58861.81
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DOI: https://doi.org/10.1023/B:JETT.0000023677.58861.81