Abstract
We investigate the linearity performance of dual-gate and fully-depleted silicon-on-insulator MOSFETs through use of 2D computer simulations, which take into account quantum mechanical considerations and non-equilibrium transport effects. We show that DG MOSFET is superior not only in terms of g m /I d characteristics, central to analog performance, but also in terms of linearity performance, by up to 5 dBm, in most operating conditions. Linearity figures of devices considered in this work range from −10 to −20 dBm, which answer the needs of mobile communication standards currently in use. We also observe that, when properly scaled, bulk MOSFETs display competitive analog performance and have third-order intercept figures very similar to SOI device. We can identify, through simulation experiments, that quantum mechanical effects have positive impact on linearity, while non-equilibrium conditions lower linearity performance. With increasing drain bias, we find that linearity saturates at a moderately low voltage (∼1 V) in all devices.
Similar content being viewed by others
References
B. Yu, IEDM Tech. Dig., 937 (2001).
H.-S. P. Wong, Proc. of ESSDERC, (2001).
R.W. Keyes, IBM J. Res. Dev., 44, 84 (2000).
P.A. Packan, Science, 285, 2079 (1999).
P.H. Woerlee et al., IEEE Trans. Electr. Dev., 1776 (2001).
T. Lee, Proc. of Symp. on RFIC, 3 (1999).
V. Kilchytska et al., IEEE Trans. Electron Dev., 50, Mar 2003, and references therein.
B. Razavi, RF Microelectronics (Prentice-Hall, 1998), ch. 2.
A. Adan et al., IEEE Trans. Elec. Dev., 881 (2002).
N. Nenadovic et al., Proc. of ESSDERC (2003).
R. van Langevelde and D.B.M. Klaassen, IEDM Tech. Dig., 313 (1997).
T. Soorapanth and T.H. Lee, available at: http://smirc.stanford. edu/papers/cancun97s-chet.pdf.
The International Technology Roadmap for Semiconductors (1999 edition).
ISE Systems Inc., TCAD Suite, http://www.ise.com
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Ma, W., Kaya, S. & Asenov, A. Study of RF Linearity in sub-50 nm MOSFETs Using Simulations. Journal of Computational Electronics 2, 347–352 (2003). https://doi.org/10.1023/B:JCEL.0000011450.37111.9d
Issue Date:
DOI: https://doi.org/10.1023/B:JCEL.0000011450.37111.9d