Abstract
MOSFETs models have been critical components for evaluation of devices design and technology. These models face the challenge of being scalable to match the available semiconductor technologies. For the 45 nm MOSFET production, dielectric and metal gates were integrated. With new high dielectric materials and thinner oxide layers, new physics effects emerged that were not considered or integrated into the early models used in circuit simulators. Here an analytical model for 45 nm MOSFETs is presented. The model includes Short Channel Effects (Channel Length Modulation, the threshold voltage variation and carriers velocity saturation). The Drain-Source current and voltage equations derived from the model are implemented as a circuit device in SPICE 3F5. A comparison between the experimental data provided by the manufacturer and the simulation results obtained with the developed model integrating the technological and electrical parameters published by Intel®, demonstrates good agreement between both sets of data.
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Rodriguez, D.E.E., Bernal, A.G.Á. (2013). Development of a Bottom-up Compact Model for Intel®’s High-K 45 nm MOSFET. In: Kim, H., Ao, SI., Rieger, B. (eds) IAENG Transactions on Engineering Technologies. Lecture Notes in Electrical Engineering, vol 170. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-4786-9_10
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DOI: https://doi.org/10.1007/978-94-007-4786-9_10
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