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Concurrent Placement and Routing in the Design of Integrated Circuits

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Abstract

For the problem arising in the design of integrated chips, an efficient heuristic approach was proposed. It unites the stages of placing the logical elements (devices) on the chip and performing their detailed routing. At that, it minimizes both the critical (maximum) delay and the chip area required for routing.

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Authors and Affiliations

  1. Russian Academy of Sciences, Sobolev Institute of Mathematics, Siberian Branch, Novosibirsk, Russia

    A. I. Erzin

  2. Sungkyunkwan University, Suwon, South Korea

    J. D. Cho

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  1. A. I. Erzin
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  2. J. D. Cho
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Erzin, A.I., Cho, J.D. Concurrent Placement and Routing in the Design of Integrated Circuits. Automation and Remote Control 64, 1988–1999 (2003). https://doi.org/10.1023/B:AURC.0000008436.55858.41

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  • DOI: https://doi.org/10.1023/B:AURC.0000008436.55858.41

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