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A Compact Four-Quadrant Floating-Gate MOS Multiplier

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Abstract

A compact, four-quadrant analog CMOS multiplier featuring wide dynamic range is presented. The capacitive voltage division obtained by the use of Floating-Gate MOS (FGMOS) transistors, and an accurate wide-swing current mirror based on active bootstrapping, allow a wide input range, low harmonic distortion, and high linearity. Simulation and measurement results for a 0.8 μm CMOS prototype demonstrate the validity of the proposed approach.

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Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, Public University of Navarra, Campus Arrosadía, E-31006, Pamplona, Spain

    Iñigo Navarro, Antonio J. López-Martín, Carlos A. de la Cruz & Alfonso Carlosena

Authors
  1. Iñigo Navarro
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  2. Antonio J. López-Martín
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  3. Carlos A. de la Cruz
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  4. Alfonso Carlosena
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Navarro, I., López-Martín, A.J., de la Cruz, C.A. et al. A Compact Four-Quadrant Floating-Gate MOS Multiplier. Analog Integrated Circuits and Signal Processing 41, 159–166 (2004). https://doi.org/10.1023/B:ALOG.0000041633.20444.cf

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  • DOI: https://doi.org/10.1023/B:ALOG.0000041633.20444.cf

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