Abstract
A new class of fully parameterizable multiple array architectures for motion estimation in video sequences based on the Full-Search Block-Matching algorithm is proposed in this paper. This class is based on a new and efficient AB2 single array architecture with minimum latency, maximum throughput and full utilization of the hardware resources. It provides the ability to configure the target processor within the boundary values imposed for the configuration parameters concerning the algorithm setup, the processing time and the circuit area. With this purpose, a software configuration tool has been implemented to determine the set of possible configurations which fulfill the requisites of a given video coder. Experimental results using both FPGA and ASIC technologies are presented. In particular, the implementation of a single array processor configuration on a single-chip is illustrated, evidencing the ability to estimate motion vectors in real-time.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards: Algorithms and Architectures, 2nd edn., Kluwer Academic Publishers, 1997.
Y. Ooi, “Motion Estimation System Design,” in Digital Signal Processing for Multimedia Systems, K.K. Parhi and T. Nishitani (Eds.), Marcel Dekker, Inc., 1999, chap. 12, pp. 299-327.
P. Pirsch, N. Demassieux, and W. Gehrke, “VLSI Architectures for Video Compression-A Survey,” Proceedings of the IEEE, vol. 83, no. 2, 1995, pp. 220-246.
S. Kittitornkun and Y.H. Hu, “Frame-Level Pipelined Motion Estimation Array Processor,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 2, 2001, pp. 248-251.
T. Komarek and P. Pirsch, “Array Architectures for Block Matching Algorithms,” IEEE Transactions on Circuits and Systems, vol. 36, no. 10, 1989, pp. 1301-1308.
L. Vos and M. Stegherr, “Parameterizable VLSI Architectures for the Full-Search Block-Matching Algorithm,” IEEE Transactions on Circuits and Systems, vol. 36, no. 10, 1989, pp. 1309-1316.
C.H. Hsieh and T.P. Lin, “VLSI Architecture for Block Matching Motion Estimation Algorithm,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 2, no. 2, 1992, pp. 169-175.
S. Chang, J.H. Hwang, and C.W. Jen, “Scalable Array Architecture Design for Full Search Block Matching,” IEEE Transactions on Circuits and Systems forVideo Technology, vol. 5, no. 4, 1995, pp. 332-343.
S.Y. Kung, VLSI Array Processors, Prentice Hall, 1988.
N. Roma and L. Sousa, “Implementation Aspects of MESA Processor,” Technical Report RT/001/2001, INESC-ID, Lisboa, Portugal, 2001.
N. Roma and L. Sousa, “A New VLSI Architecture for Full Search Block Matching,” in IFIP International Conference on Very Large Scale Integration (VLSI-SoC'2001), Montpellier, France, 2001, pp. 213-218.
Xilinx, “Virtex 2.5V Field Programmable Gate Arrays-Product Specification,” Xilinx Inc., 2001.
VST, “Diplomat-25 Standard Cell Library-0.25 µm UMC Process,” Virtual Silicon Technology Inc., 1999.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Roma, N., Sousa, L. Automatic Synthesis of Motion Estimation Processors Based on a New Class of Hardware Architectures. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 34, 277–290 (2003). https://doi.org/10.1023/A:1023204620405
Published:
Issue Date:
DOI: https://doi.org/10.1023/A:1023204620405