Abstract
Motion estimation is the cornerstone of main video compression standards, which are based on the reduction of the temporal redundancy between consecutive frames. Although the mechanism is simple, the best method, Full Search, uses a brute-force approach which is not suited for real-time applications. This work introduces a high performance architecture for performing on-the-fly full-search block matching estimation in FPGA devices, which has been modeled using C++ programming language and synthesized with Vivado HLS for a Xilinx ZC706 prototyping board. The architecture is based on a dataflow datapath and it is configurable, enabling a fast and easy exploration of the solution space. On-board results achieve a maximum performance of 743 fps, 247 fps and 110 fps for VGA, HD and FHD video resolutions, respectively, for a typical macroblock size of \(16 \times 16\) pixels and a search area of \(\pm 16\) pixels.
This research is partially funded by the Ministry of Economy and Competitiveness (MINECO) of the Spanish Government under project PLATINO (grant number TEC2017-86722-C4-R4), the Regional Government of Castilla-La Mancha under project SymbIoT (grant number SBPLY/17/180501/000334) and the EU’s Horizon 2020 programme under project SHAPES (GA N\(^{o}\) 857159).
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Barba, J., Caba, J., Escolar, S., Torre, J.A.D.L., Rincón, F., López, J.C. (2021). A Dataflow Architecture for Real-Time Full-Search Block Motion Estimation. In: Derrien, S., Hannig, F., Diniz, P.C., Chillet, D. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2021. Lecture Notes in Computer Science(), vol 12700. Springer, Cham. https://doi.org/10.1007/978-3-030-79025-7_16
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