Abstract
A method is considered for ensuring resistance to failure in operational computer memory devices by utilizing linear correcting codes with a posteriori correction of multiple errors. The proposed method makes it possible to extend the correcting possibilities of the code, i.e., to determine the configuration of any error with the minimum code redundancy and the lowest hardware and software costs.
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Pavlov, Ar.A., Pavlov, A.A. Methods for Correcting Multiple Errors of Information Storage Devices Used in Microprocessor Facilities of Measurement Technology (a discussion). Measurement Techniques 45, 141–145 (2002). https://doi.org/10.1023/A:1015583503896
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DOI: https://doi.org/10.1023/A:1015583503896