Abstract
Disturbances are special type of faults that are unique to flash memories. Causes of the disturbances are defects within the insulating layers of the memory element. These defects result in abnormal behavior of a memory cell under specific conditions. This paper describes characteristics of these defects as well as their manifestation as DC-Programming, DC-Erasure, and Drain Disturbance. We develop fault models to capture the behavior of faulty flash memories. We introduce three different fault models based on the underlying defects in a memory cell. These models are: Simple, Exclusive and General Fault model. Further, we develop test algorithms that detect disturbance faults under each of the fault models. The test algorithms reported in this paper for the simple fault model for each type of disturbance require optimal number of program, read, and flash operations; where as the algorithms for the remaining two fault models require near optimal number of these operations.
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Mohammad, M.G., Saluja, K.K. & Yap, A.S. Fault Models and Test Procedures for Flash Memory Disturbances. Journal of Electronic Testing 17, 495–508 (2001). https://doi.org/10.1023/A:1012868605214
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DOI: https://doi.org/10.1023/A:1012868605214