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An Algebraic Approach to Formal Verification of Microprocessors

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Abstract

In this letter we report the formal verification of microprocessors. After we describe algebraically a bit-sliced microprocessor at both function and logic levels, we apply the symbolic manipulation of Mathematica.

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References

  1. R.E. Bryant and Y. Chen, “Verification of Arithmetic Circuits with Binary Moment Diagrams,” in Proc. DAC, 1995.

  2. K. Hirabayashi, “A Method of Formal Verification of Cryptographic Circuits,” J. Electronic Testing, Vol. 3, pp. 321-322, 1998.

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  3. T. Sridhar and J.P. Hayes, “A Functional Approach to Testing Bit-Sliced Microprocessors,” IEEE Trans. on Computers, Vol. C-30, pp. 563-571, 1981.

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  4. S. Wolfram, Mathematica: A System for Doing Mathematics by Computer, 2nd ed., Wolfram Research Inc., 1991.

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Authors and Affiliations

  1. Toshiba Techno Center Inc., Hamamatsucho 1-18-16, Tokyo, 105-0013, Japan

    Kanji Hirabayashi

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  1. Kanji Hirabayashi
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Hirabayashi, K. An Algebraic Approach to Formal Verification of Microprocessors. Journal of Electronic Testing 17, 543–544 (2001). https://doi.org/10.1023/A:1012824822961

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  • DOI: https://doi.org/10.1023/A:1012824822961

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