Skip to main content
Log in

Detectability Conditions of Full Opens in the Interconnections

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Opens in interconnection paths disconnect the driven gate(s) from the driving gate. Detectability conditions to test full opens in interconnections are investigated. It has been found that the detectability of this defect depends strongly on the signals at the driving gate and coupling lines. Three possible situations are analyzed. The first is when there is full controllability of both the signal driving the open and the signal(s) at the coupling line(s). Then, the cases of partial and low controllability of the signals are analyzed. Conditions for reliable detection of this defect by logic and IDDQ testing have been determined. In addition, it has been found that the detectability of interconnection opens depends on the metal level where the signals are laid-out. Routing design for testability techniques are recommended for some interconnection opens non detectable by either a stuck-at based or IDDQ testing. Experimental data on intentionally designed defective circuit is presented.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. K. Baker, G. Gronthoud, M. Lousberg, I. Schanstra, and C. Hawkins, “Defect-Based Delay Testing of Resistive Vias-Contacts: A Critical Evaluation,” Int. Test Conference, 1999, pp. 467-476.

  2. V.H. Champac, J.A. Rubio, and J. Figueras, “Electrical Model of the Floating Gate Defect in CMOS ICs: Implications on IDDQ Testing,” IEEE Trans. on Computer-Aided Design, vol. 13,no. 3, pp. 359-369, March 1994.

    Google Scholar 

  3. V.H. Champac and A. Zenteno, “Detectability Conditions for Interconnection Open Defect,” 18th IEEE VLSI Test Symposium, May 2000, pp. 305-311.

  4. D.B.I. Feltham and W. Maly, “Physically Realistic Fault Models for Analog CMOS Neural Networks,” IEEE Journal of Solid-State Circuits, Sept. 1991.

  5. C.F. Hawkins, J.M. Soden, R.R. Fritzemeier, and L.K. Horning, “Quiescent Power Supply Current Measurement for CMOS IC Detection,” IEEE Transactions on Industrial Electronics, vol. 36,no. 2, pp. 211-218, May 1989.

    Google Scholar 

  6. C.F. Hawkins et al., “Defect Classes—An Overdue Paradigm for CMOS IC Testing,” International Test Conference, 1994, pp. 413-425.

  7. C.F. Hawkins et al., “IC Reliability and Test: What Will Deep Submicron Bring,” IEEE Design & Test, vol. 16,no. 2, pp. 84-91, 1999.

    Google Scholar 

  8. C.L. Henderson, J.M. Soden, and C.F. Hawkins, “The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits,” Int. Test Conference, 1991, pp. 302-310.

  9. S. Johnson, “Residual Charge on the Faulty Floating Gate MOS Transistors,” Int. Test Conf., 1994, pp. 555-561.

  10. H. Konuk, “Fault Simulation of Interconnect Opens in Digital CMOS Circuits,” International Conference in Computer Aided-Design, 1997.

  11. H. Konuk and F.J. Ferguson, “An Unexpected Factor int Testing for CMOS Opens: The Die Surface,” IEEE VLSI Test Symposium, 1996.

  12. H. Konuk and F.J. Ferguson, “Oscillation and Sequential Behavior Caused by Opens in the Routing in Digital CMOS Circuits,” IEEE Trans, on Computer-Aided Design, vol. 17,no. 11, pp. 1200-1210, Nov. 1998.

    Google Scholar 

  13. H. Konuk, F.J. Ferguson, and T. Larrabee, “Charge-Based Fault Simulation for CMOS Networks Breaks,” IEEE Transactions on Computer-Aided Design, vol. 15,no. 12, pp. 1555-1567, Dec. 1996.

    Google Scholar 

  14. J.C.M. Li and E.J. McCluskey, “Testing for Tunneling Opens,” Proceedings of the International Test Conference, 2000, pp. 95-104.

  15. O.V. Maiuri and W.R. Moore, “Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm,” IEEE VLSI Test Symposium, 1998, pp. 22-27.

  16. W. Maly, P.K. Nag, and P. Nigh, “Testing Oriented Analysis of CMOS ICs with Opens,” Proc. Int. Conf. on Computer-Aided Design, 1988, pp. 344-347.

  17. R. McGowen and F.J. Ferguson, “Incorporating Physical Design-For-Test Into Routing,” International Test Conference, 1997, pp. 685-693.

  18. W. Moore, G. Gronthoud, K. Baker, and M. Lousberg, “Delay-Fault Testing and Defects in Deep Sub-Micron ICs—Does Critical Resistance Really Mean Anything?,” Proceedings of the International Test Conference, 2000, pp. 85-94.

  19. W. Needham, C. Prunty, and E.H. Yeoh, “High Volume Microprocessor Test Escapes, An Analysis of Defects Our Tests are Missing,” Int. Test Conference, 1998, pp. 25-34.

  20. M. Renovell and G. Cambon, “Topology Dependence of Floating Gate Faults in MOS Circuits,” Electronics Letters, vol. 22,no. 3, pp. 152-153, Jan. 1986.

    Google Scholar 

  21. B.J. Sheu, W.-J. Hsu, and P.K. Ko, “An MOS Transistor Charge Model for VLSI Design,” IEEE Transactions on Computer-Aided Design, vol. 7,no. 4, pp. 520-527, April 1988.

    Google Scholar 

  22. A.D. Singh and H. Rasheed, “IDDQ Testing of CMOS Opens: An Experimental Study,” International Test Conference, 1995, pp. 479-489.

  23. M. Renovell, A. Ivanov, Y. Bertrand, F. Azais, and S. Rafiq, “Optimal Conditions for Boolean and Current Detection of Floating Gate Faults,” Int. Test Conference, 1999.

  24. K.M. Thompson, “Intel and the Myths of Test,” IEEE Design & Test, vol. 13,no. 1, pp. 79-81, 1996.

    Google Scholar 

  25. N.H. Weste and K. Eshraghian, Principles of CMOS VISI Design, A System Perspective, Reading, MA: Addison-Wesley, 1985.

    Google Scholar 

  26. H. Xue, C. Di, and J.A.G. Jess, “Probability Analysis for CMOS Floating Gate Faults,” European Design and Test Conference, 1994, pp. 443-448.

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Zenteno, A., Champac, V.H. & Figueras, J. Detectability Conditions of Full Opens in the Interconnections. Journal of Electronic Testing 17, 85–95 (2001). https://doi.org/10.1023/A:1011179007753

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1011179007753

Navigation