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A 3 V Wideband CMOS Switched-Current A/D-Converter Suitable for Time-Interleaved Operation

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Abstract

The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f in = 1.83, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio (SNDR) = 46.5dB at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 μm CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR ≥ 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.

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Authors and Affiliations

  1. Microelectronics X/FE, Ericsson Radio Systems AB, S-164 80, Stockholm, Sweden

    Bengt E. Jonsson

  2. Electronic System Design Laboratory, KTH-Electrum, Royal Institute of Technology, S-164 40, Stockholm, Sweden

    Hannu Tenhunen

Authors
  1. Bengt E. Jonsson
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  2. Hannu Tenhunen
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Jonsson, B.E., Tenhunen, H. A 3 V Wideband CMOS Switched-Current A/D-Converter Suitable for Time-Interleaved Operation. Analog Integrated Circuits and Signal Processing 23, 127–139 (2000). https://doi.org/10.1023/A:1008393909629

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