Abstract
This paper describes an 8-bit 40 MS/s pipeline A/D converter suitable for WCDMA receiver applications. Small power consumption is achieved by using 1.5 bit/stage pipeline architecture and by scaling the capacitor values along the converter. Digital correction allows also to use very low power dynamic comparators. The multiplying D/A converters (MDACs) utilize a modified folded cascode amplifier. The circuit is designed and fabricated in a 0.5 μm CMOS technology. The measured DNL is 0.85 LSB and INL 1.91 LSB. The converter achieves over 48 dBc SFDR and more than 41 dBc SNDR dissipating 61 mW from a 2.7 V supply.
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Sumanen, L., Waltari, M. & Halonen, K. An 8-bit 40 MS/s Pipeline A/D Converter for WCDMA Testbed. Analog Integrated Circuits and Signal Processing 22, 41–49 (2000). https://doi.org/10.1023/A:1008320026490
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DOI: https://doi.org/10.1023/A:1008320026490