Abstract
We present two novel reconfiguration schemes, L/U reconfiguration and its generalization, band reconfiguration, to achieve graceful degradation for general microarchitecture datapaths. Upon detection of a datapath fault, hardware and algorithmic reconfigurations are performed dynamically through operation rescheduling and hardware rebinding. Instead of a complete shuffling, the proposed scheme perturbs the original schedule and binding in a systematic fashion. This regularity of the scheme allows well-structured design planning for the controller and the datapath. The underlying microarchitecture supporting such reconfiguration schemes is briefly outlined. Experimental evidence indicates negligible performance and small hardware overheads.
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Orailoğlu, A. On-Line Fault Resilience Through Gracefully Degradable ASICs. Journal of Electronic Testing 12, 145–151 (1998). https://doi.org/10.1023/A:1008298226600
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DOI: https://doi.org/10.1023/A:1008298226600