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Scalable Test Generators for High-Speed Datapath Circuits

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Abstract

This paper explores the design of efficient test sets and test-pattern generators for on-line BIST. The target applications are high-performance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of carry-lookahead, most existing BIST methods are unsuitable for these applications. High-level models are used to identify potential test sets for a small version of the circuit to be tested. Then a regular test set is extracted and a test generator TG is designed to meet the following goals: scalability, small test set size, full fault coverage, and very low hardware overhead. TG takes the form of a twisted ring counter with a small decoder array. We apply our technique to various datapath circuits including a carry-lookahead adder, an arithmetic-logic unit, and a multiplier-adder.

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Authors and Affiliations

  1. Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, The University of Michigan, 1301 Beal Avenue, Ann Arbor, MI, 48109-2122

    Hussain Al-Asaad & John P. Hayes

  2. Electrical and Electronics Department, General Motors R&D Center, 30500 Mound Road, Warren, MI, 48090-9055

    Brian T. Murray

Authors
  1. Hussain Al-Asaad
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  2. John P. Hayes
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  3. Brian T. Murray
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Al-Asaad, H., Hayes, J.P. & Murray, B.T. Scalable Test Generators for High-Speed Datapath Circuits. Journal of Electronic Testing 12, 111–125 (1998). https://doi.org/10.1023/A:1008242108853

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