Abstract
Previous work in automata theory has shown how to eliminate sequential redundancy from networks of FSMs by finding sequences of inputs and outputs which are never communicated between components of the network. This paper shows that behavior automata—finite-state machines whose inputs and outputs are incompletely scheduled—exhibit similar properties. Using the behavior FSM (BFSM) as a model for scheduling, we show how to identify and eliminate both input and output scheduling don‘t-cares. When a scheduling don‘t-care is eliminated from a network of BFSMs, the register-transfer implementation is guaranteed not to suffer from the corresponding don‘t-care sequence. A definition of scheduling don‘t-cares improves our understanding of the foundations of high-level synthesis and the relationship between high-level and sequential optimization. In practice, scheduling don‘t-care elimination is a powerful tool for eliminating redundancy early in the design process.
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Wolf, W. Redundancy Removal during High-Level Synthesis Using Scheduling Don‘t-Cares. Journal of Electronic Testing 11, 211–225 (1997). https://doi.org/10.1023/A:1008214405542
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DOI: https://doi.org/10.1023/A:1008214405542