Skip to main content
SpringerLink
Log in

Designing FPGAs and Reconfigurable SoCs Using Methods of Program Analysis and Prototyping

  • Published:
Russian Microelectronics Aims and scope Submit manuscript

Abstract

This paper describes approaches and methods for software circuit prototyping of field-programmable gate arrays (FPGAs) and reconfigurable systems-on-a-chip (RSoC). Software circuit prototyping is a new stage in the design flow for FPGAs and reconfigurable SoCs in contrast to the classical FPGA-based prototyping using ready-made FPGA chips. It allows to evaluate the efficiency of the user circuit design implementation and select the basic chip architecture before its tape-out because of the computer-aided design (CAD) tools promptly adapting to any changes in the structure, circuitry and layout of a basic chip. The flexible and dynamic software customization to maintain the required FPGA or RSoC architecture is provided by the developed formalized description of the basic circuit, which is used in CAD and is represented in this paper. This formalized description can be used both for the analysis of the basic chip and for the analysis of a user circuit design implemented on an FPGA or RSoC.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1.
Fig. 2.

Similar content being viewed by others

REFERENCES

  1. Krasnikov, G.Ya., Enns, V.I., et al., Development and manufacture of a library of analog IP blocks for use as part of very large-scale integrated circuits “System on a Chip” at a domestic enterprise using technology with minimum topological norms of no more than 0.18 microns, Research Report, Moscow: Zelenograd, 2017.

    Google Scholar 

  2. Enns, V.I., SoC, BMK or FPGA: Choice of digital integrated circuit option, Kompon. Tekhnol., 2018, no. 4, pp. 100–102.

  3. Krasnikov, G.Ya., The capabilities of microelectronic processes with 5 nm critical dimension and less, Nanoindustriya, 2020, vol. 13, no. S5-1 (102), pp. 13–19.

  4. Krasnikov, G.Ya., Panasenko, P.V., Volosov, V.A., and Shcherbakov, N.A., Trends in the development of technology of complex functional heterointegrated ECB, in Tr. Mezhdunarodn. foruma 'Mikroelektronika-2018', 4-ya Mezhdunarodnaya nauchnaya konferentsiya 'Elektronnaya komponentnaya baza i mikro elektronnye moduli' (Proceedings of the International Forum Microelectronics-2018, 4th International Conference on Electronic Component Base and Microelectronic Modules), Alushta: Tekhnosfera, 2018, pp. 341–344.

  5. Li, X., Yang, H., and Zhong, H., Use of VPR in design of FPGA architecture, in Proceedings of the 8th International Conference on Solid-State and Integrated Circuit Technology, 2006, Shanghai, China: IEEE, 2006, pp. 1880–1882.

  6. Luu, J. et al., VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling, in ACM Transactions on Reconfigurable Technology and Systems (TRETS), Monterey, CA: ACM, 2008, pp. 133–142.

    Google Scholar 

  7. Parvez, H. et al., A new coarse-grained FPGA architecture exploration environment, in Proceedings of the 2008 International Conference on Field-Programmable Technology, Taipei, Taiwan: IEEE, 2008, pp. 285–288.

  8. Kannan, P., Balachandran, S., and Bhatia, D., On metrics for comparing routability estimation methods for FPGAs, in Proceedings of the 2002 Design Automation Conference, New Orleans, LA, USA: IEEE, 2002, pp. 70–75.

  9. Gao, Hai-Xia et al., A novel Monte-Carlo method for FPGA architecture research, in Proceedings of the 7th International Conference on Solid-State and Integrated Circuits Technology, 2004, Bejing, China: IEEE, 2004, pp. 1944–1947.

  10. Doman, D., Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon, New York: Wiley, 2012.

    Book  Google Scholar 

  11. Amos, D., Lesea, A., and Richter, R., FPGA-Based Prototyping Methodology Manual: Best Practices in Design-for-Prototyping, USA: Synopsys Press, 2011.

    Google Scholar 

  12. Ohba, N. and Takano, K., An SoC design methodology using FPGAs and embedded microprocessors, in Proceedings of the 41st Annual Design Automation Conference DAC'04, New York: Assoc. Comput. Machinery, 2004, pp. 747–752.

  13. Chochaev, R.Zh., Zheleznikov, D.A., Ivanova, G.A., Gavrilov, S.V., and Enns, V.I., FPGA routing architecture estimation models and methods, Izv. Vyssh. Uchebn. Zaved., Elektron., 2020. vol. 25, no. 5, pp. 410–422.

    Google Scholar 

  14. Gandhare, S. and Karthikeyan, B., Survey on FPGA architecture and recent applications, in Proceedings of the 2019 International Conference on Vision Towards Emerging Trends in Communication and Networking ViTECoN, Vellore, India, 2019, pp. 1–4.

  15. MAX II Device Handbook, Altera Corp. www.intel. com/content/dam/www/programmable/us/en/pdfs/ literature/hb/max2/max2_mii5v1.pdf. Accessed April 1, 2021.

  16. UltraScale Architecture Configurable Logic Block User Guide, Xilinx Inc. www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf. Accessed April 01, 2021.

  17. ProASIC3 nano FPGA Fabric User’s Guide, Microsemi Corp., http://www.ibselectronics.com/ibsstore/ datasheet/Microsemi/PA3_nano_UG.pdf. Accessed April 01, 2021.

  18. GDSII™ Stream Format Manual, Release 6.0, Calma Comp., http://bitsavers.informatik.uni-stuttgart.de/pdf/ calma/GDS_II_Stream_Format_Manual_6.0_Feb87.pdf. Accessed April 01, 2021.

  19. Gavrilov, S.V., Zheleznikov, D.A., Zapletina, M.A., Khvatov, V.M., Chochaev, R.Zh., and Enns, V.I., Layout synthesis design flow for special-purpose reconfigurable systems-on-a-chip, Russ. Microelectron., 2019, vol. 48, no. 3, pp. 176–186.

    Article  Google Scholar 

  20. Vasil’ev, N.O., Tiunov, I.V., and Ryzhova, D.I., Method of logical resynthesis of circuits in the design route on FPGA, Probl. Razrab. Persp. Mikro- Hanoelektron. Sist., 2020, no. 4, pp. 39–44.

  21. Ivanova, G.A., Ryzhova, D.I., Gavrilov, S.V., Vasil’ev, N.O., and Stempkovskii, A.L., Methods and algorithms for the logical-topological design of microelectronic circuits at the valve and inter-valve levels for promising technologies with a vertical transistor gate, Russ. Microelectron., 2019, vol. 48, no. 3, pp. 167–175.

    Article  Google Scholar 

  22. Gavrilov, S.V., Zheleznikov, D.A., Chochaev, R.Zh., and Khvatov, V.M., Partitioning algorithm based on simulated annealing for reconfigurable systems-on-chip, Probl. Razrab. Persp. Mikro- Nanoelektron. Sist., 2018, no. 1, pp. 199–204.

  23. Gavrilov, S.V., Zheleznikov, D.A., Chochaev, R.Zh., and Enns, V.I., The modification of simulated annealing-based placement algorithm for reconfigurable systems-on-chip, Elektron. Tekh., Ser. 3: Mikroelektron., 2018, no. 4 (172), pp. 55–61.

  24. Zapletina, M.A., Zheleznikov, D.A., and Gavrilov, S.V., The hierarchical approach to island style reconfigurable system-on-chip routing, Probl. Razrab. Perspekt. Mikro- Nanoelektron. Sist., 2020, no. 3, pp. 16–21.

  25. Francis, R.J., A tutorial on logic synthesis for lookup-table based FPGAs, in Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design ICCAD’92, Washington, DC, USA: IEEE Comput. Soc., 1992, pp. 40–47.

  26. Brglez, F., Bryan, D., and Kozminski, K., Combinational profiles of sequential benchmark circuits, in Proceedings of the IEEE International Symposium on Circuits and Systems, Portland, OR, USA, 1989, vol. 3, pp. 1929–1934.

  27. Usselmann, R., AC 97 Controller IP Core. https:// opencores.org/projects/ac97. Accessed April 3, 2021.

Download references

Author information

Authors and Affiliations

  1. AO Molecular Electronics Research Institute (AO MERI), 124460, Zelenograd, Moscow, Russia

    V. I. Enns & V. G. Kurbatov

  2. Institute for Design Problems in Microelectronics, Russian Academy of Sciences (IDPM RAS), 124365, Zelenograd, Moscow, Russia

    S. V. Gavrilov & V. M. Khvatov

Authors
  1. V. I. Enns
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. S. V. Gavrilov
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. V. M. Khvatov
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. V. G. Kurbatov
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding authors

Correspondence to V. I. Enns, S. V. Gavrilov or V. M. Khvatov.

Additional information

The text was translated by the authors.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Enns, V.I., Gavrilov, S.V., Khvatov, V.M. et al. Designing FPGAs and Reconfigurable SoCs Using Methods of Program Analysis and Prototyping. Russ Microelectron 50, 426–438 (2021). https://doi.org/10.1134/S106373972106007X

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1134/S106373972106007X

Search

Navigation