Modelling and Impact Analysis of Antipode Attack in Bufferless On-Chip Networks

Abstract

With advancements in VLSI technology, Tiled Chip Multicore Processors (TCMP) with packet switching Network-on-Chip (NoC) have evolved as the backbone of modern data intensive parallel systems. Manufacturers are looking at the prospect of using several third-party Intellectual Property (IP) cores in their TCMP designs due to strict time-to-market restrictions. Outsourcing IP from vendors across the world exposes System-on-Chip (SoC) designs to malicious implants such as Hardware Trojans (HTs). The performance of entire system is adversely affected by the presence of malicious HT in NoC routers, which can negatively disrupt communication between tiles. Generally, in buffered NoC, hardware trojans affect flits when they are in input buffers. Hardware trojans in bufferless NoC is a less explored area. In this paper, we model an HT that leads to antipode attack, which can occur on Permutation Deflection Network (PDN) of a bufferless router. In a bufferless router such as CHIPPER architecture, only the highest priority flit gets productive port, while other flits may or may not get productive port depending on port availability, leading to deflections. The modelled trojan misroutes all flits of HT-infected router to non-productive ports without modifying the flit control field. We investigate the effects of such an intermittent HT and analyse its effects at NoC level in terms of performance metrics such as average flit latency, deflection rate, throughput and router link utilisation. Experimental evaluations conducted on an $8\times 8$ bufferless mesh NoC indicate that the modelled HT degrades network performance due to increased flit deflections and traffic across central routers which impacts system reliability.