Abstract
This paper proposes a ninelevel switchedcapacitor stepup inverter (9LSUI) which can achieve a quadruple voltage gain with single dc source. Differing from other switchedcapacitor inverters, the voltage stress of switches is effectively reduced due to the elimination of Hbridge, and the peak inverse voltage of all switches is kept within 2V_{dc}. In addition, the proposed inverter is able to integrate inductive load, and the capacitor voltage selfbalancing can be achieved without any auxiliary circuits. Moreover, the topology structure can be flexibly extended to raise the output levels, and the peak inverse voltage of switches can remain constant with the increase of submodules in the extended structure. Comprehensive comparisons are performed to verify the outstanding advantages of the proposed inverter. Finally, the steadystate and dynamic performance of the proposed inverter is validated through an experimental prototype, and the experimental results are provided to prove the theoretical analysis.
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1 Introduction
Nowadays, multilevel inverters (MLIs) have been widely applied in many areas, such as electric vehicles (EVs), flexible ac transmission systems and motor drives [1,2,3]. Comparing with the conventional twolevel inverter, MLIs work better in: reducing the dv/dt on switches; improving output power quality; reducing electromagnetic interference; requiring smaller filters [4].
In general, traditional MLIs are classified into three categories: neutralpointclamped (NPC) [5, 6]; flying capacitor (FC) [7, 8]; cascaded Hbridge (CHB) [9, 10]. NPC and FC inverters can obtain the desired output voltage by using clamping diodes and floating capacitors. However, the challenge of balancing the capacitor voltage complicates the control strategy along with the increase of the output levels. The CHB inverters consist of Hbridge units, which have the advantages of modular, scalable design and simple control. However, these topologies require multiple dc sources and have no voltage gain, which can limit the applications [11].
Furthermore, the dc sources such as photovoltaic panels, fuel cells and batteries of electric vehicles have low voltage [12], and conventional multilevel inverters suffer from the lack of voltage gain and the unbalance of capacitor voltage. In order to overcome these problems, a dcdc boost converter is inserted into the front end of the inverter [13]. However, the cascade device will raise power losses and reduce the efficiency of the inverter [14]. To improve the boosting capability, the Zsource techniques have been used in MLIs. However, the extra inductors can increase the volume and cost of inverters. Moreover, the number of output levels has been limited [15,16,17].
Another solution is the switchedcapacitor multilevel inverters (SCMLIs) which have no requirement for magnetic components such as inductors and transformers. SCMLIs are able to achieve multilevel output and boost voltage through a switchedcapacitor circuit. In addition, the capacitor voltage can be selfbalanced without any auxiliary circuits. The stepup switchedcapacitor inverter proposed in [18] can output fivelevel voltage with single dc source. The other single input SC inverter proposed in [19] for highfrequency application employs two capacitors to generate ninelevel output voltage. However, the maximum output voltage is only twice the input voltage. The ninelevel SC inverter proposed in [20] also has a twice voltage gain.
In order to promote the voltage gain, a generalized inverter has been proposed in [21] to obtain a higher output voltage. Similarly, to increase the flexibility of SCMLIs regarding the output levels and voltage gain, two extendable SCMLIs have been proposed in [22] and [23]. The stepup inverter in [22] reduces the number of power switches, but the ability to integrate inductive loads is lost. For the SC inverter proposed in [23], the capacitors can be charged by a binary asymmetrical pattern, which can significantly raise the number of output levels. However, one of the common shortcomings of the above inverters is that the use of a backend Hbridge increases the total voltage stress of devices.
The high peak inverse voltage (PIV) of switches can limit the applications of inverters. The accumulation of voltage stress can be avoided by cascading multiple SC inverters [24]. However, multiple isolated dc sources and numerous power components are needed. In addition, the SCMLIs proposed in [25] and [26] eliminate the backend Hbridge to reduce the PIV. However, both inverters employ numerous switches, which is not conducive to simplify the control strategy, and will lead to an increase of power losses. In [27], a ninelevel quadrupleboost inverter with an inherent ability to reverse the polarity of the output voltage has been presented. However, there are two switches that need to withstand the peak value of the output voltage. The stepup SC inverter proposed in [28] reduces the total standing voltage (TSV) of switches. However, numerous capacitors will lead to an increase of system volume and weight.
Considering the aforementioned challenges, this paper proposes a ninelevel switchedcapacitor inverter (9LSUI) with low voltage stress. The eminent characteristics of the proposed 9LSUI are as follows:

(1)
Ninelevel output voltage can be achieved with only two capacitors and single dc source.

(2)
The proposed inverter has a quadruple voltage gain with low voltage stress.

(3)
The PIV of each switch is kept within 2V_{dc}, which can significantly reduce the TSV of inverter.

(4)
An extendable structure in which the PIV of all switches can be kept within 3V_{dc}.

(5)
Capacitor voltage can be selfbalanced without involving additional controls.
Next section introduces the circuit design and modulation strategy of the proposed inverter. Section 3 presents the comparison between the proposed topology and other inverters. Section 4 demonstrates the steadystate and dynamic experimental results, and conclusion is obtained in Sect. 5.
2 Proposed 9LSUI
2.1 Circuit Design
Figure 1 depicts the proposed 9LSUI, in which ten power switches S_{1} ~ S_{10} and two capacitors C_{1} and C_{2} constitute the SC unit to achieve a multilevel output and voltage boost. Additionally, the complementary switch pairs (S_{L}, \(\overline{S} _{{\text{L}}}\)) and (S_{R}, \(\overline{S} _{{\text{R}}}\)) constitute two halfbridges to reverse the polarity of the output voltage. The proposed inverter employs single dc source which is set as V_{dc}. All switches are equipped with an antiparallel diode except for S_{10}. Capacitors C_{1} and C_{2} can be charged to V_{dc} and 2V_{dc}, respectively. The inverter can output nine levels: 0, ± V_{dc}, ± 2V_{dc}, ± 3V_{dc}, ± 4V_{dc}. Hence, the proposed topology achieves a quadruple voltage gain.
The proposed inverter has an excellent characteristic of low voltage stress. As shown in Fig. 1, X is the ratio of PIV to V_{dc}, which can visually indicate the maximum stress of each switch. It can be seen that the PIV of most switches is V_{dc}, only switches S_{8} ~ S_{10}, S_{R} and \(\overline{S} _{{\text{R}}}\) withstand the voltage 2V_{dc} which is half of the peak output voltage. Therefore, it is worth noting that the features of high boosting factor and low voltage stress make the topology fit for medium and highpower applications with low input voltage.
2.2 Operating Principle
The operating principle of switches and capacitors are shown in Table 1. Where “0” and “1” indicate the off and on states of switches, “C”, “D” and “–” denote the charging, discharging and idle states of capacitors.
Detailed nine operating states and current paths of the proposed inverter are demonstrated in Fig. 2, where the blue highlight and purple highlight lines are the charging current paths of capacitors and the reverse current paths. It can be seen that capacitor C_{1} can be charged to V_{dc} in parallel with dc source when the output voltages are 0, V_{dc} and ± 3V_{dc}. Capacitor C_{2} can be charged to 2V_{dc} in parallel with dc source and capacitor C_{1} when the output voltages are 2V_{dc} and –V_{dc}. The connections of the dc source and capacitors can be changed through the ON/OFF states of switches, so as to achieve ninelevel output voltage and quadruple voltage gain.
2.3 Modulation Strategy
Various modulation techniques have been applied to multilevel inverters. In this paper, the phase disposition pulse width modulation (PDPWM) is selected for the proposed 9LSUI due to its simplicity and low total harmonic distortion (THD) [28].
As shown in Fig. 3, eight carrier signals e_{1} ~ e_{8} are compared with a sinusoidal reference signal e_{s} to generate eight pulse signals u_{1} ~ u_{8}. The gate drive signals v_{GS1} ~ v_{GSR} of the switches can be obtained through the logical combination of u_{1} ~ u_{8}. The logical combination can be expressed as
The modulation index M for the 9LSUI is defined as
where A_{s} and A_{c} are the amplitudes of the reference signal and carrier signals. The range of M is 0 < M ≤ 1. The inverter can output different levels with the change of M between 0 and 1.
3 Capacitance and Power Losses
3.1 Design of Capacitor
The voltage fluctuation range of capacitors should be maintained within an acceptable range to improve voltage quality. The capacitor voltage ripple is related to the maximum continuous discharge of the capacitor. Therefore, the effect of the capacitor voltage ripple on the output voltage can be reduced effectively when the proper value of the capacitance is selected.
It can be seen from Fig. 2 and Table 1, C_{1} will be in discharging state when output voltages are V_{dc} and 2V_{dc} in the negative half cycle, and C_{2} will be in discharging state when the proposed 9LSUI outputs 3V_{dc} and 4V_{dc}. As shown in Fig. 3, the maximum continuous discharging intervals of C_{1} and C_{2} are [t_{7}, t_{10}] and [t_{9}, t_{12}]. In fact, C_{1} and C_{2} are in alternate charging and discharging for part of the time in these two intervals, such as C_{1} in the interval [t_{7}, t_{8}]. The most extreme case that ignores the charging time of capacitors is considered in the following analysis. The time t_{7}, t_{9}, t_{10} and t_{12} in Fig. 3 are calculated as follows
where f_{s} is the frequency of the sinusoidal reference wave. Assuming the load is pure resistive. Therefore, the maximum continuous discharging amount ΔQ_{C1} of C_{1} within [t_{7}, t_{10}] can be calculated as
The maximum continuous discharging amount ΔQ_{C2} of C_{2} within [t_{9}, t_{12}] is calculated as
where I_{load} is the amplitude of the load current. Assuming k% is the constant describes the maximum acceptable voltage ripple, the capacitances of C_{1} and C_{2} can be determined as
3.2 Calculation of Losses
3.2.1 Switching Losses
The switching losses of MLIs occur during the turnon and turnoff period of power switches due to the inherent switching delay [23]. It is known that the voltage and current of switches exhibit a linear approximation during the switching period. Therefore, the turnon losses (P_{sw,on,i}) and the turnoff losses (P_{sw,off,i}) of the ith involved power switch can be calculated by
where f_{sw} is the switching frequency, v_{s} and i_{s} present the voltage and current of switch when the switching state changes, V_{on,i} and V_{off,i} are the onstate and offstate voltage of the ith switch, I_{on,i} and I_{off,i} are the onstate and offstate current that across the ith switch, t_{on} and t_{off} are the time of turnon and turnoff. Therefore, the total switching losses P_{sw} of the proposed inverter can be obtained as
3.2.2 Conduction Losses
The conduction losses are related to the parasitic resistance of power devices in current paths, including the conduction resistance R_{on} of switches, the internal resistance R_{D} of antiparallel diodes and the equivalent series resistance R_{ESR} of the capacitors.
The equivalent resistance for each level is listed in Table 2. According to Fig. 3 and Table 2, in the interval [0, t_{1}], the load current flows through three switches and three diodes (four switches and two diodes) when the output voltage is 0 (V_{dc}). Therefore, the energy loss E_{loss1} during the interval [0, t_{1}] can be calculated as
where i_{load} is the load current, R_{on} is the conduction resistance of switches and R_{D} is the internal resistance of antiparallel diodes.
Similarly, the conduction losses in other inverters ([t_{1}, t_{2}][t_{13}, t_{14}]) are also can be calculated according to Eq. (21). The total conduction losses P_{cond} as the proposed 9LSUI can be calculated as
where f_{s} is the frequency of the sinusoidal reference wave.
3.2.3 Capacitor Ripple Losses
The ripple loss P_{rip} is caused by the voltage fluctuation of capacitor. The voltage ripple ΔV_{rip,Ci} of the capacitor C_{i} is obtained by
where i_{Ci}(t) is the current across capacitor, the interval [t, t +] is the discharging period of C_{i}. For the proposed 9LSUI, [t_{8}, t_{9}] and [t_{9}, t_{12}] are the maximum discharging intervals of C_{1} and C_{2}. The ripple losses P_{rip} can be calculated as
Therefore, the total losses P_{loss} of the proposed 9LSUI can be calculated as
Finally, the efficiency of the ninelevel inverter can be expressed as
where η and P_{o} are the efficiency and output power of the proposed inverter.
4 Topology Extension and Comparisons
The proposed 9LSUI can be extended with multiple SC units, which can generate more output levels and achieve higher voltage gain. In order to further evaluate the superiority of the proposed topology, a comprehensive analysis and comparison with other recently SCMLIs have been implemented.
4.1 Extended Structure
The extended structure of the proposed 9LSUI is shown in Fig. 4. It can be seen that each two SC units are in a backtoback connection through a power switch pairs P_{i1} and P_{i2} (i = 1, 2, …, n1). Notice that these switch pairs have a complementary operation with each other to avoid the shortcircuit problem. In the extended topology, n dc sources are used and the voltage is V_{dc}. Therefore, the number of capacitors (N_{Cap}) and switches (N_{SW}) can be expressed as
In this configuration, the voltage of the capacitor C_{i1} remains as V_{dc} and the capacitor C_{i2} is charged to 2V_{dc}. The PIV of P_{i1} and P_{i2} is kept within 3V_{dc} in the extended structure. Therefore, the number of output levels (N_{L}), the peak value of the output voltage (V_{o, max}) and the TSV for the switches can be obtained as:
4.2 Comparison of Ninelevel Inverters
In this section, to evaluate the performance of the proposed 9LSUI, a comprehensive comparison with other topologies is made in Table 3. The comparison focuses on the numbers of dc sources (N_{Source}), capacitors (N_{Capacitor}), switches (N_{Switches}) and diodes (N_{Diodes}). Furthermore, the PIV of semiconductors (switches and diodes), the TSV_{pu} of semiconductors, the voltage gain and the use of Hbridge are also considered. The terms related to TSV_{pu} and voltage gain are defined as
where V_{o_max} and V_{dc} are the maximum output peak voltage and the dc input voltage.
According to Table 3, the proposed inverter requires minimum capacitors, which helps to reduce the volume and weight of the inverter. Moreover, compared with other inverters, the proposed topology employs single dc source and two capacitors to achieve quadruple voltage gain, while the boosting factor in [19] and [20] is 2. Although the inverters in [22] and [23] use fewer switches, they all require Hbridge to shift output voltage polarity. Moreover, the large number of diodes used in [22] may limit its capacity of integrating inductive loads.
The PIV of the switches is important role to evaluate the performance of MLIs. The comparison shows that the PIV of the switches is only 2V_{dc}. Although the inverter in [25] has lower PIV, the use of numerous switches will lead to a high cost. A significant feature of the proposed inverter is low TSV_{pu}, which also credits to the low PIV of switches. The inverter in [28] has the lowest TSV, but the use of four capacitors increases the volume and cost.
The comparison between the suggested extended structure and other inverters is performed at the output levels of (2 m + 1) or m. Table 4 and Fig. 5. show the comparison results, the proposed extended structure employs less components (capacitors, switches and diodes). Moreover, the proposed structure does not need extra diodes and has the minimum TSV_{pu}. In a word, the proposed topology has obvious advantages in promoting voltage gain, reducing the number of components and voltage stress of the switches.
5 Simulation and Experiment Analysis
5.1 Simulation Results
In order to examine the performance of the proposed inverter, a simulation model of ninelevel switchedcapacitor inverter is established in MATLAB/Simulink. The simulation parameters are shown in Table 5.
The simulation results are shown in Fig. 6. It can be seen that the proposed inverter can output ninelevel voltage and achieve a quadruple voltage gain. The capacitor voltages are selfbalanced with low voltage ripple.
When the modulation index is 0.9, the Fast Fourier Transform (FFT) of the output voltage is shown in Fig. 7. It can be seen that the THD is 15.18%, and the 40th harmonic component is larger than the others because the carrier frequency is 2 kHz. The low THD can also simplify the design of the filter.
5.2 Experimental Results
To verify the practicability and effectiveness of the proposed 9LSUI, an experimental prototype has been built as shown in Fig. 8. The components and parameters of the model are shown in Table 6. The experiments examine the steadystate performance and dynamic responses of the proposed topology under several different conditions.
Figure 9 shows the steadystate experiment results and efficiency curve. The output voltage and load current are shown in Fig. 9a. It can be seen that the amplitude of output voltage is 120 V, which verifies that the proposed inverter can achieve a voltage gain of 4. Figure 9b presents the output voltage and load current when the inductive load is integrated. The load current appears as a sinusoidal waveform due to low THD. The voltages of C_{1} and C_{2} under the R & L load are shown in Fig. 9c. It can be observed that C_{1} and C_{2} are charged to 28.66 V and 57.65 V. Moreover, the capacitor voltage fluctuates periodically within 5 V, which verifies the selfbalancing ability of the proposed inverter. Figure 9d shows the theoretical efficiency and experimental efficiency of the proposed inverter under different output power. It can be seen that the 9LSUI has a great performance.
Figure 10 shows the voltage stress of different switches. The peak inverse voltages of the switches S_{1} ~ S_{7}, S_{L}, and \(\overline{S} _{{\text{L}}}\) are V_{dc}, and the peak inverse voltages of the switches S_{8} ~ S_{10}, S_{R}, and \(\overline{S} _{{\text{R}}}\) are 2V_{dc}. Table 7 presents the steadystate experimental results. The experimental results are in good agreement with the previous theoretical analysis, which proves that the proposed inverter has the characteristics of low voltage stress across switches.
Figure 11 and Table 8 present the dynamic experimental results with the change of M. Figure 11a–c show the dynamic responses when the modulation ratio M varies from 0.9 to 0.7, 0.7 to 0.4 and then 0.4 to 0.2. It can be seen that the number of output levels will reduce with the decrease of M. Meanwhile, the amplitude of the load current also decreases accordingly. The waveforms quickly reach new steadystates after these changes, which is in good agreement with the theoretical analysis and design requirements.
Figures 12a, b are the dynamic responses when the dc source varies from 10 to 30 V and from 30 to 10 V. In Fig. 12, the amplitude of the output voltage gradually rises from 40 to 120 V when the input voltage increases. Meanwhile, the voltage of C_{1} rises from 10 to 30 V, and the voltage of C_{2} rises from 20 to 60 V. It can be seen from Fig. 12b that the variations of load current and voltage are opposite to the ones in Fig. 12a when the input voltage decreases. Figures 12c, d are the dynamic responses when the load varies from noload to resistive load (50 Ω), and then to resistiveinductive load (50 Ω15 mH). The output voltage remains constant, and the load current varies instantaneously with the change of load, and then reaches a new steadystate.
In summary, the experimental results of the proposed 9LSUI validate the previous theoretical analysis. The capacitor voltage selfbalancing can be achieved under steadystate and dynamic conditions, which verifies the practicability and effectiveness of proposed inverter.
6 Conclusion
The paper presents a switchedcapacitor stepup inverter, which can generate nine output levels and achieve quadruple voltage gain without Hbridge. In addition, the proposed 9LSUI has voltageselfbalance ability without any auxiliary circuits, and the peak inverse voltage of all switches is kept within 2V_{dc}. Moreover, the extended structure of the proposed inverter can generate more output levels, while the PIV of all switches is kept within 3V_{dc}. The comparison results with other inverters show that the proposed inverter has the advantages of reducing the components, raise the voltage gain, and lowering the TSV of devices. An experimental prototype is implemented to verify the effectiveness and feasibility of proposed 9LSUI. The experimental results indicate that the proposed topology performs well in different conditions.
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Acknowledgements
This work was supported in part by the National Natural Science Foundation of China under Grant 51507155, in part by the Youth Key Teacher Project of Henan Universities under Grant 2019GGJS011, and in part by the Key R&D and Promotion Special Project of Henan Province under Grant 222102520001.
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Wang, Y., Ye, J., Wang, K. et al. A NineLevel SwitchedCapacitor StepUp Inverter with Low Voltage Stress. J. Electr. Eng. Technol. 18, 1147–1159 (2023). https://doi.org/10.1007/s4283502201187z
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DOI: https://doi.org/10.1007/s4283502201187z