A current mode instrumentation amplifier with high common-mode rejection ratio designed using a novel fully differential second-generation current conveyor

Abstract

This study presents a high common-mode rejection ratio (CMRR), and high power-supply rejection ratio (PSRR) current-mode instrumentation amplifier (CMIA) to overcome the limitations of existing differential voltage second-generation current conveyors (DVCCII)-based CMIAs in achieving high CMRR. The design is based on a fully differential second-generation current conveyor block with a novel circuit design following by a current subtracting stage. The CMIA is designed and laid out in 130 nm CMOS technology operating under ± 1.2 V supply voltage in Cadence software. The post-layout simulation results show that the CMIA achieves low-frequency voltage and current CMRR- BW of 228.8 dB–10 kHz and 246 dB–10.6 kHz, respectively, with PSRR + /PSRR- of 108.2 dB/99.7 dB, power consumption of 507 µW, and a core area of 0.0015 mm². The unique quality of the circuit is that, it does not need well-matched active blocks, but inherently improves CMRR, bandwidth, and PSRR; hence it gains an excellent choice for integration.

Article highlights

• Highly accurate amplifier is designed to detect very weak signals of information (such as biomedical signals), and amplify them for further processing.

• This circuit has two different input terminals to accommodate both voltage and current signals.

• The final circuit is very small and consumes low power. Thus, it is a good choice for seamless integration to develop portable systems.

1 Introduction

In the last decades, due to the increasing demand for portable and battery powered equipment and advances in technology downscaling trend, researchers and designers of analog processors have been encountered with some major challenges in the design of low-power low-voltage (LPLV) circuits and systems [1,2,3]. Current-mode (CM) signal processing was envisioned as a promising solution to design small and fast LPLV circuits and thus gained more popularity [3,4,5,6,7]. The major advantages of CM processors over the voltage-mode (VM) processors include wide dynamic range and bandwidth (BW), simple circuitry, high speed, low supply voltage and power consumption [4,5,6]. The incorporation of a high-CMRR instrumentation amplifier (IA) is crucial in many analog/mixed-mode systems such as data acquisition, biomedical circuits and control systems in order to suppress the unwanted common-mode signals along with the desired signals of information [1,2,3,4,5]. Several different voltage-mode instrumentation amplifiers (VMIA) have been reported so far, but they seriously suffer from gain-BW trade-off, and need for precisely matched resistors to achieve high CMRR [8,9,10]. As a result, the conventional VMIAs have been gradually replaced by current-mode instrumentation amplifiers (CMIA) [11,12,13].

The CMIA structures can be divided into two main configurations based on input signals as: the low input impedance CMIAs compatible with current input signals [14,15,16] and the high input impedance ones compatible with voltage input signals [8, 9]. The low input impedance CMIAs utilize the advantages of CM signal processing and have attracted great interests especially after the introduction of CM alternative of Wheatstone bridge (Azka cell) [17]. However, most of the reported CMIAs are of the high input impedance ones [8, 9] whose structures are classified into second-generation current conveyors (CCII)-based CMIAs [15, 19] and current sensing-based CMIAs [8, 20].

CCIIs are active blocks that have been used in designing different analog circuits and systems such as amplifiers [18,19,20], oscillators [21], analog switches [22, 23], and active filters [24, 25] to grant the benefits of CM circuit design. Although CMRR performance of CCII-based CMIAs is not limited by matching resistors to improve CMRR, they need well-matched active block pairs to achieve higher CMRR. For example, two topologies of CCII-based CMIAs by Wilson [15] and Kaulberg [26] which are suitable for floating loads and both floating and grounded loads, respectively, are reported. Based on experimental results in [15] and [26], CMRR performance of the CMIAs was controlled entirely by the quality and matching of CCII blocks; also, high differential gain and BW was achieved simultaneously while by varying the resistive load, CMRR was almost unchanged. To avoid this matching constraint, differential voltage second-generation current conveyors (DVCCII)-based CMIAs were introduced [10, 20]. Although DVCCII-based CMIAs contain only one active block, they are compatible with only voltage input signals. Among all of the reported CMIAs, those based on fully differential second-generation current conveyors (FDCCIIs) [13, 14] have been of great interest since they employ only one active block and thus no critical component matching conditions are required. Moreover, FDCCII-based CMIAs are compatible with differential input terminals that can be adapted to both voltage and current input signals and differential output terminals.

This paper proposes a FDCCII-based CMIA benefiting from the following features: a) the circuit is designed based on CM circuit techniques and benefits from all advantages of CM signal processing. b) The CMIA has been designed based on only one block of FDCCII with novel circuit design; thus, there is no need for well-matched active blocks to achieve high CMRR. c) Despite the conventional VMIA, in the designed CMIA for a good range of output resistive load there is almost no dependency between gain and BW meaning that the differential gain can increase while the BW remains unchanged. d) Also, the designed CMIA contains one low-impedance differential input in addition to another high-impedance one to process and amplify both current and voltage input signals, respectively. e) Finally, a current subtracting stage has been added to the main block to further improve CMRR and realize a high CMRR CMIA. The rest of the paper is organized as follows: in section II an overview of the FDCCII building blocks is provided. Transistor-level implementation of the CMIA and a detailed design description are presented in section III. Post-layout simulation results along with Process, Voltage, and Temperature (PVT) effect on the performance of the proposed FDCCII and the CMIA, implemented in TSMC 130-nm CMOS technology, are presented in section IV. Finally, section V concludes this work.

2 Fully differential second-generation current conveyors blocK

Functional block diagram with the directions of current and voltage along with the operational matrix of a typical FDCCII are shown in Fig. 1 and Eq. (1), respectively [5]. FDCCII is a current-mode active building block consists of two consecutively connected voltage and current buffers with six terminals, conventionally denoted as Y₊, Y_–, X₊, X_–, Z₊, and Z_–, as illustrated in Fig. 1. Ideally, there is a unity differential voltage gain across X and Y terminals (V_xd/ V_yd = 1) and a unity differential current gain between Z and X terminals (I_zd/ I_xd = 1). The ideal input impedance at Y, input (output) impedance at X and output impedance at Z nodes are infinite, zero (infinite), and infinite, respectively. Practically, the non-ideal impedances at any abovementioned terminals, results in undesirable effects on the functionality of FDCCII.

Fig. 1

Block diagram of a typical FDCCII.

The setup block diagrams of the implemented CMIA including the FDCCII followed by a current subtraction stage for voltage and current inputs are shown in Fig. 2a and b, respectively. The current subtracting circuit provides a single-ended topology enabling the CMIA to drive grounded loads.

$$\left[ \begin{gathered} {\text{I}}_{{{\text{y}} + }} \hfill \\ {\text{I}}_{{{\text{y}} - }} \hfill \\ {\text{V}}_{{{\text{x}} + }} \hfill \\ {\text{V}}_{{{\text{x}} - }} \hfill \\ {\text{I}}_{{{\text{z}} + }} \hfill \\ {\text{I}}_{{{\text{z}} - }} \hfill \\ \end{gathered} \right] = \left[ {\begin{array}{*{20}c} 0 \\ 0 \\ 1 \\ {\begin{array}{*{20}c} 0 \\ 0 \\ 0 \\ \end{array} } \\ \end{array} \begin{array}{*{20}c} { 0} \\ { 0} \\ { 0} \\ {\begin{array}{*{20}c} {{ } - 1} \\ {{ }0} \\ {{ }0} \\ \end{array} } \\ \end{array} \begin{array}{*{20}c} { 0} \\ { 0} \\ { 0} \\ {\begin{array}{*{20}c} {{ }0} \\ {{ }1} \\ {{ }0} \\ \end{array} } \\ \end{array} \begin{array}{*{20}c} {\begin{array}{*{20}c} {{ }0{ }} & 0 & 0 \\ \end{array} } \\ { \begin{array}{*{20}c} {0{ }} & 0 & 0 \\ \end{array} } \\ { \begin{array}{*{20}c} {0{ }} & 0 & 0 \\ \end{array} } \\ {\begin{array}{*{20}c} {\begin{array}{*{20}c} {{ }0} \\ {{ }0} \\ {{ } - 1} \\ \end{array} } & {\begin{array}{*{20}c} 0 \\ 0 \\ 0 \\ \end{array} } & {\begin{array}{*{20}c} {0{ }} \\ {0{ }} \\ {0{ }} \\ \end{array} } \\ \end{array} } \\ \end{array} } \right]\left[ {\begin{array}{*{20}c} {\begin{array}{*{20}c} {{\text{V}}_{{{\text{y}} + }} } \\ {{\text{V}}_{{{\text{y}} - }} } \\ \end{array} } \\ {{\text{I}}_{{{\text{x}} + }} } \\ {\begin{array}{*{20}c} {{\text{I}}_{{{\text{x}} - }} } \\ {{\text{V}}_{{{\text{Z}} + }} } \\ {{\text{V}}_{{{\text{Z}} - }} } \\ \end{array} } \\ \end{array} } \right]$$

(1)

Fig. 2

CMIA configuration for a voltage input signals and b current input signals

Also, the current subtractor cancels out the common-mode components of the output current signals at Z terminals resulting in a significant improvement in CMRR, which is a key characteristic of an IA.

The operation of the CMIA can be described based on the type of the input signal as follows. First, as it is shown in Fig. 2a, for voltage-input configuration, the unity gain voltage buffer between Y and X terminals transfers input voltage signals from Y to X [5] and assuming an ideal current conveyor, X₊ and X_- are receiving identical common mode signals. Thus, no common mode current signal is produced through the external resistor, R_ext. As a result, no common-mode current signal conveys from X to Z terminals through the current buffer, and hence no common-mode current passes through the resistive load (R_L). However, in real case, the existence of the common-mode signals cannot be ignored.

In case of current-input configuration, the current signal is applied to the low-impedance differential input terminal of X (Fig. 2b) and Y terminals are grounded. The common-mode components of the current signal are conveyed from X to Z through the unity-gain current buffer. Assuming a perfectly matched current mirrors in the current subtractor, any potentially common-mode current components can be removed at the final output using the current subtractor leading to higher voltage and current CMRR.

3 Current-mode instrumentation amplifier circuit

The design is mainly focusing on improving CMRR, targeting high-performance CMIA. The CMOS realization of the designed CMIA is shown in Fig. 3 consisting of the FDCCII and the current subtracting stage. Like most of the FDCCIIs [14, 27], the voltage tracking performance depends on the matching tolerances between output currents of two transconductors (M₁–M₈). Transistors M₁–M₂ and M₃–M₄ are the differential pairs of the input transconductor stages that share active loads of M₂₅–M₂₆. The differential pairs must be tightly matched to achieve a unity differential voltage gain from Y to X terminals. Using translinear loops in X terminals (including M_T1–M_T8), the internal impedances of X nodes get reduced resulting in very low impedance input terminals with higher absorption of current signal. A common-mode feed forward (CMFF) approach has been employed using M₅-M₈ to decrease common-mode voltage/current signals at nodes B, C, X₊, and X_-. In common mode condition, any common mode signals at Y (X) input terminals generate current signals in M₂ and M₃ (M₁ and M₄) and the same current signals will be generated in M₆ and M₇ (M₅ and M₈). Then, M₂₃-M₂₆ generate the same current signals with negative sign (as M₂₃–M₂₆ are NMOS devices) and add them to B and C. Thus, at node B and C the effect of common mode current signals is removed following by the cancellation of the effect of common mode signals at X nodes. The CMFF technique makes voltage/current signals at B (C) and X₊ (X_-) to remain unchanged in the presence of common mode signals resulting in CMRR improvement.

Fig. 3

Schematic of the designed CMIA

To avoid amplification of common-mode voltage signals at M₁₁ and M₁₂ drains (D and E), another CMFF circuit was employed using current mirrors M₁₁-M₁₃ and the pair of M₂₉- M₃₀. Any common mode signals at B and C generate common mode current signals in M₂₇ and M₂₈. Then, M₂₉–M₃₀ apply the same current signals (as the current signals in M₂₇ and M₂₈) with negative sign to current mirror M₁₁–M₁₃ and node D and E. Thus, the common-mode current signals of D and E nodes are cancelled following by the cancellation of common mode signals at X nodes and further improvement of CMRR. M₃₁-M₃₄ are current buffer stages between X and Z terminals that should be matched to achieve a unity differential current gain. At Z terminals, the simple current mirror M₁₈–M₂₀ along with transistors M₃₅–M₃₆, act as a CMFF technique. These transistors remove common-mode currents passing through Z terminals by adding the same current signals with negative sign to Z terminals resulting in current and voltage CMRR improvement.

The bias voltage of the current and voltage buffers is provided by V_ocm. This voltage is generated by the CMFB (Common Mode Feed Back) block consisting of the current mirror M₁₆-M₁₇ and differential pair M₃₇–M₃₈. The function of the CMFB block is to set the common-mode voltages of X nodes to zero using negative feedback approach. By considering the internal mismatches in the FDCCII, the presence of common mode signals at Y terminals results in nonidentical common mode signals at X₊ and X_-. As a result, a common mode current signals flows through the external resistances R_ext due to the difference between X₊ and X_- potentials. This current signal changes the common-mode voltage of node V_icm. (M₃₇ gate) This voltage variation, stimulates differential pair M₃₇–M₃₈ to change M₃₈ drain voltage (V_ocm) using M₁₆ and M₁₇. Variation in V_ocm changes common-mode currents passing through M₁₄–M₁₅ using a negative feedback connection that finally prevents the common-mode currents to pass through M_T1–M_T2. As a result, the common mode signals at X₊ and X_- are removed.

The current subtracting stage consists of three improved Wilson current mirrors (M₃₉-M₅₆) with cascade active loads (M₅₇–M₆₄) [27] as it is shown in Fig. 3. The first current mirror (M₃₉-M₄₁, M₄₈–M₅₀) sends I_z+ to the final output (node out in Fig. 3). The second and the third current mirrors (M₄₂- M₄₄, M₅₁- M₅₃, and M₄₅-M₄₇, M₅₄-M₅₆) convey -I_z- to the output.

$$\begin{gathered} I_{z + ,diff} \cong - I_{z - ,diff}, I_{z + ,com} \cong I_{z - ,com} \left\{ \begin{gathered} I_{out,com} = I_{z + ,com} - I_{z - , com} \cong 0 \hfill \\ I_{out,diff} = I_{z + ,diff} - I_{z - , diff} \cong 2I_{z + ,diff} \hfill \\ \end{gathered} \right\} \hfill \\ \hfill \\ \end{gathered}$$

(2)

In common mode condition, ${I}_{z+,com} \cong {I}_{z-,com}$ and in differential mode condition ${I}_{z+,diff} \cong {-I}_{z-,diff}.$ At the output node,${I}_{out}={I}_{z+}- {I}_{z-}$ flows through the resistive load connected to the output (R_L). This means (as expressed in Eq. 2), ideally the common-mode current signals of Z₊ and Z_- are removed at the output current flow through R_L, while the differential ones are doubled. This results in the improvement of differential gain and reduction in common mode gain which can be translated into a significant improvement in CMRR. In the following sections, the performance of the CMIA with and without current subtracting stage is studied in detail to investigate the effect of adding the current subtracting stage on the performance of the CMIA.

The voltage and current CMRRs are obtained using Eq. (3) and Eq. (4) where ${\varepsilon }_{1(2)}$ and ${{\varepsilon }^{^{\prime}}}_{1(2)}$ are the current tracking errors of the current subtracting stage for differential and common-mode signals, respectively and β_i for i = 1–9 are defined gains and errors (the detailed derivation is described in the Appendix). Also, the internal resistance of X terminals can be expressed using Eq. (5).

$$CMRR_{{\text{V}}} \cong \frac{{{ }\beta_{7} \left( {CMRR_{{V_{XY} }} \times \left( {\beta_{6} - \frac{{\beta_{5} \beta_{7} }}{{\beta_{1} }}} \right) - \beta_{4} } \right)\left( {R_{ext} + r_{x} } \right) + \beta_{3} \beta_{{4{ }}} \alpha_{2} { })}}{{\beta_{3} \left( {\beta_{8} - \beta_{9} } \right)\left( {R_{ext} + r_{x} } \right)}} \times \frac{{1 + \varepsilon_{1\left( 2 \right)} }}{{1 + \varepsilon^{\prime}_{1\left( 2 \right)} }}$$

(3)

$$CMRR_{{\text{I}}} = \frac{{\left( {\beta_{7} \left( {\left( {CMRR_{{V_{XY} }} \times \beta_{6} - \frac{{\beta_{5} \beta_{7} }}{{\beta_{1} }}} \right) - \beta_{4} } \right)\left( {R_{ext} + r_{x} } \right) + { }\beta_{3} \beta_{{4{ }}} \alpha_{2} } \right)}}{{\left( {CMRR_{{V_{XY} }} \times \beta_{6} - \frac{{\beta_{5} \beta_{7} }}{{\beta_{1} }}} \right) \times \beta_{3} \left( {\beta_{8} - \beta_{9} } \right) \times \left( {R_{ext} + r_{x} } \right)}} \times \frac{{\left( {\beta_{6} - \frac{{\beta_{5} \beta_{7} }}{{\beta_{1} }}} \right) \times \left( {1 + \varepsilon_{1\left( 2 \right)} } \right)}}{{1 + \varepsilon^{\prime}_{1\left( 2 \right)} }}$$

(4)

$$r_{x + \left( - \right)} = \frac{1}{{g_{{m{\text{MT}}1\left( 3 \right) + }} g_{{m{\text{MT}}5\left( 7 \right)}} }}$$

(5)

4 Post-layout simulation results and discussion

The proposed circuit is designed and laid out in TSMC 130 nm single-poly, eight-metal CMOS process and its performance is evaluated using CADENCE software tool after parasitic (RC) extraction. Figure. 4 shows the CMIA layout which occupies an active area of only 37 × 42 µm². The transistor dimensions used in this design are listed in Table 1. In this simulation, the following parameters are set: R_ext = 450 Ω, R_L = 1 kΩ, the bias voltage applied to the gates of M₉, M₁₀, MT₁₁, and M_T12 (V_BB) is 0.6 V, and the bias voltage of the current subtracting stage (V_SB) is 0.5 V, such that each transistor of the input differential pairs (M₁–M₈) have a current bias of approximately 4.2 µA.

Fig. 4

The CMIA layout

Table 1 Transistor Sizes

4.1 Core fully differential second-generation current conveyors characterization

In this section, the performance of the stand-alone FDCCII is evaluated to ensure that the performance of the main building block is sufficient to support the CMIA operation. The post-layout and Monte Carlo (MC) simulation results on the most important design metrics of the FDCCII block including common mode and differential mode voltage and current gains between X and Y as well as Z and X, respectively, the BW of the differential gains, the internal impedance in X and Z terminals, and power consumption for 1000 iterations are given in Table 2. For differential signals, the FDCCII achieves an input voltage tracking error of ~ 0.009 from Y terminal to X terminal ($1 - \frac{{V_{xd} }}{{V_{yd} }}$). In addition, the output differential current tracking error from X to Z_+(-) terminal ($1 - \frac{{I_{z + \left( - \right)} }}{{I_{xd} }}$) is approximately 0.024. The FDCCII also has a low impedance of 16.1 Ω at current input terminal of X₊ (X_-) and a high output impedance of ~ 687 kΩ at terminal Z₊ (Z_-). The frequency response of X terminal internal resistance, R_x, is shown in Fig. 5 which shows a low-frequency value of 16.1 Ω with a 3-dB BW of 2.53 MHz. MC simulation results demonstrate that the common-mode voltage and current gains are more susceptible to the device mismatches than the differential ones.

Table 2 FDCCII characteristics

Fig. 5

X-terminals intrinsic resistance

4.2 Current-mode instrumentation amplifier characterization

The frequency responses of voltage and current CMRRs of the CMIA consisting of the FDCCII followed by the current subtracting stage are shown in Fig. 6. The designed CMIA achieves a high voltage CMRR of 228.8 dB with 3-dB BW of 10.0 kHz and a high current CMRR of 246 dB with 3-dB BW of 10.6 kHz at a supply voltage of ± 1.2 V. Figure 7a shows voltage and current CMRR magnitude at DC over different R_ext. An average voltage and current CMRR magnitude of ⁓220 and ⁓240 dB are obtained, respectively, when R_ext varies from 400 Ω to 500 Ω. Differential voltage and current gain-bandwidth products (GBPs) with different resistive loads (R_L) changing from 1 kΩ to 300 kΩ are shown in Fig. 7b. Also, Fig. 7c and d shows the differential voltage gain and current gain of the CMIA over different R_L. From Fig. 7b, it is obvious that for 1 kΩ ≤ R_L < 32 kΩ, both voltage and current GBPs were linearly increasing with the output load, indicating that the differential voltage/current gain increases with an increase in R_L, while the BW remains almost constant as shown in Fig. 7c and d. In this range of R_L, the trade-off between gain and BW that inherently exists in voltage-mode circuits is almost negligible. For R_L ≥ 32 kΩ, the compromise between gain and BW develops, leading to a decrease in GBPs rate. For R_L ≥ 100 kΩ, the CMIA behaves similar to a voltage mode circuit as the GBPs remain almost constant with increase in R_L suggesting that the magnitude of the differential gains is inversely proportional to the BW. The magnitude of differential gain, common mode gain, and CMRR at DC frequency over different R_L for the CMIA with voltage and current input signals, are shown in Fig. 7e and f, respectively. Based on the figures, it is obvious that by increasing the R_L, the differential gain magnitude increased, but increasing R_L resulted in the decrease of common mode gain magnitude; as a result, the CMRR for both voltage and current signals remained almost constant over different R_L. Figure 7g and h shows the voltage and current CMRR magnitude at DC over different V_BB, changing from 0.95 × V_BB (∆V_BB = − 5%) to 1.05 × V_BB (∆V_BB =  + 5%) while ∆V_SB is 0%, + 5%, or − 5%, respectively. Based on Fig. 7g and h, the voltage and current CMRR magnitudes are > 180 dB while bias voltages are changing by ± 5% and this magnitude of CMRRs are close to Monte Carlo results shown in Fig. 8. Also, the current CMRR magnitude is more sensitive to variations in the bias voltages when compared to that of voltage CMRR.

Fig. 6

Voltage and current CMRR when VDD = ±1.2 V, R_L=1kΩ, and R_ext = 450 Ω for the proposed CMIA

Fig. 7

a Voltage and current CMRR magnitude at DC over different Rext varying from 400 to 500 Ω. b Voltage and current GBP c differential voltage gain, and d differential current gain for different R_L from 1 kΩ to 300 kΩ. e and f the magnitude at DC frequency of differential, common mode and CMRR over different R_L for the CMIA with voltage and current input signals, respectively. g Voltage and h current CMRR magnitude at DC over different V_BB and V_SB. Note: in b–h R_ext is 450 Ω

Fig. 8

Monte Carlo results for a voltage CMRR, b voltage CMRR 3dB-Band Width; c current CMRR and d current CMRR 3dB-Band Width for the proposed CMIA

The impact of local process variations on voltage and current CMRRs of the CMIA and their BWs is investigated using Monte Carlo (MC) analysis with 1000 runs. The obtained results are shown in Fig. 8 indicating that both the current and voltage CMRRs have almost equal mean values of ~ 185 dB with ~ 11.3 kHz of 3 dB-BWs. The positive and negative PSSR curves (PSRR₊ and PSRR₋) are depicted in Fig. 9. The PSRR₊ and PSRR − are 108.2 dB and 99.7 dB at DC frequencies, respectively. Figure 10 illustrates the input referred noise of the CMIA from 10 to 100 kHz. The rms value of the input referred noise is 3.61 μV, integrated from 10 to 1 kHz. The simulation results also indicate that the output offset of the CMIA is 1.67 µV. Table 3 summarizes the performance of the CMIA and compares it with the single FDCCII block. In the case where the current subtractor is detached from the FDCCII outputs, and two load resistors of 1 kΩ are connected to Z₊ and Z₋, while other circuit parameters and simulation conditions remain unchanged. The results verify the effectiveness of incorporation of the current subtracting stage in the CMIA as it enhances current and voltage CMRRs by 131 and 110 dB, respectively, while increasing power consumption by only 12%.

Fig. 9

Simulated PSRR₊ and PSRR_- of the CMIA

Fig. 10

Simulated input-referred noise of the CMIA

Table 3 CMIA characteristics with and without current subtractor

4.3 Process, voltage, and temperature variations' influence

In this section the robustness of the proposed CMIA against process, voltage, and temperature (PVT) variations is investigated in details. The simulated differential voltage gain from X to Y and differential current gain from Z to X for the FDCCII block in different process corners including Typical-Typical (TT), Slow-Slow (SS), Fast-Slow (FS), Slow-Fast (SF), and Fast–Fast (FF) are shown in Fig. 11a and b, respectively. In Fig. 11a and b, the worst corners of FS and FF shows a maximum of ~ 10 and ~ 5% variation in differential voltage and current gains, respectively, when compared to TT condition. In addition to the FDCCII, the aforementioned five process corners for the simulated voltage and current CMRRs of the CMIA are shown in Fig. 11c and d, respectively. For the CMIA, the average low-frequency voltage/current CMRR over different process corners is 204.1 dB/200.2 dB while a maximum variation of 16.5%/32.9%, with respect to the TT corner, is observed at FF/FF corner. Moreover, 3 dB-BW for the voltage/current CMRR remains above 7.94 kHz/7.82 kHz in the worst corner (SS/FS).

Fig. 11

Corner analyses for a differential voltage gain from X to Y and b differential current gain from Z to X of the FDCCII block. Corner analyses for c Voltage CMRR, and d current CMRR of the proposed CMIA

The performance summary of the CMIA over temperature range of − 25 °C to 75 °C at ± 1.2 V supply voltage is shown in Table 4. A minimum CMRR of ~ 170 dB is achieved for both current and voltage signals at − 25 °C which is quite comparable to that of the recently reported CMIA designs [14, 19, 27]. Despite the CMRR magnitude, the voltage/current CMRR 3 dB-BW is less vulnerable to the temperature changes as it remains above 10 kHz/9.5 kHz over the entire temperature range.

Table 4 CMIA performance over temperature and different supply voltages

In addition to ± 1.2 V supply voltage, the CMIA is characterized for lower supply voltages of ± 1.0 V, ± 0.8 V, and even ± 0.6 V at room temperature as it is shown in Table 4. The CMIA exhibits nearly similar CMRRs’ performances with ± 1 V and ± 0.8 V while the CMRRs’ BWs are approximately scaled down with the voltage supply. Also, it shows 15.2%/17.8% and 13.1%/23.3% voltage/current CMRR reduction when voltage supply is reduced from ± 1.2 V to ± 1 V and ± 0.8 V, respectively. While a voltage/current CMRR of 185.6 dB/191.9 dB is obtained from ± 0.6 V supply voltage (which corresponds to only 18.8%/21.9% reduction in voltage/current CMRR compared to ± 1.2 V nominal supply voltage at room temperature), the power consumption significantly decreases from 507.2 to 72.8 µW which can be translated into ~ 86% reduction, as it is shown in Table 4.

Table 5 summarizes the CMIA performance and compares it to previously published designs. The novel CMIA exhibits superior performance in terms of CMRR for both voltage and current inputs without the need for accurately matched components. To make a fair comparison, a figure of merit (FoM) is defined in Eq. 6.

$$FoM = \max \left(\frac{{CMRR_{V} \times BW_{{{\text{CMRR}}_{V} }} }}{P},\frac{{CMRR_{I} \times BW_{{{\text{CMRR}}_{I} }} }}{P}\right)$$

(6)

Table 5 A comparison table summarizing the performance metrics of this work with others

In Eq. 6, $CMRR_{{\text{V}}}$ and $CMRR_{{\text{I}}}$ are low-frequency voltage and current CMRRs, respectively, $BW_{{{\text{CMRR}}_{{\text{V}}} }}$ and $BW_{{{\text{CMRR}}_{{\text{I}}} }}$ are their corresponding 3-dB BWs (in kHz), and $P$ is the power consumption (in µW). The FoM reflects the ability of a CMIA to reject the frequency components of common-mode signals at a given power consumption. To provide a fair comparison, same voltage/current CMRR and BW are assumed in FoM calculations when either of the data was not reported.

5 Conclusion

In this paper, a novel high CMRR CMIA in 130-nm CMOS technology is proposed. The CMIA includes an FDCCII to accurately convey the differential signals which is followed by a current subtracting stage to remove the common-mode components from the output current. The employed CMFB and CMFF techniques along with an accurate common-mode current subtraction stage allows the CMIA to achieve a high CMRR for both types of input signals. Post-layout simulation results have demonstrated the robustness of the CMIA against PVT variations. The CMIA’s ability to efficiently operate with 50% of its nominal supply voltage as well as the small silicon area, and low power dissipation makes it suitable for battery-powered and portable health monitoring systems. Future research focuses on realizing the circuit using the same technology and demonstrate its high CMRR performance and feasibility for fabricating standalone health monitoring devices such as highly sensitive portable stethoscopes for measuring electroencephalography (EEG) signals.

Appendix

This section describes the governing equations of the proposed FDCCII. In the following calculations, R_ext has not been considered.

1.1 Voltage gain between X and Y

If differential input voltage of $V_{{Y_{diff} }} = V_{{Y_{ + } }} - V_{{Y_{ - } }}$ ($V_{{Y + { }}} = { } - V_{{Y - { }}} = \frac{{V_{{Ydiff{ }}} }}{2}$) is applied to Y-terminals, Eq. (7) to Eq. (8) could be concluded. The drain currents of M₁ (M₂) and M₅ (M₆) can be written as Eq. (7), where V_sM1 and V_sM5 are the source voltages of M₁ and M₅.

$$i_{ac1\left( 2 \right)} = g_{m1\left( 2 \right)} \left( {V_{{X\left( Y \right) + { }}} - V_{sM1} } \right),\,i_{ac5\left( 6 \right)} = g_{m5\left( 6 \right)} \left( {V_{{Y\left( X \right) - { }}} - V_{sM5} } \right)$$

(7)

Applying KCL at the source of M₁, we arrive at:

$$\begin{array}{*{20}l} {\frac{{ - V_{sM1\left( 5 \right)} }}{{r_{{o9\left( {10} \right)}} }}{ }} \hfill & { = \left( {\left( {g_{m1\left( 6 \right)} + { }g_{m3\left( 8 \right)} } \right) \times \left( {V_{X + \left( - \right)} - V_{sM1\left( 5 \right)} } \right)} \right) + \left( {\left( {g_{m2\left( 5 \right)} + { }g_{m4\left( 7 \right)} } \right) \times \left( {V_{Y - \left( + \right)} - V_{sM1\left( 5 \right)} } \right)} \right)} \hfill \\ {V_{sM1\left( 5 \right)} } \hfill & { = \frac{{ - \left( {\left( {g_{m1\left( 6 \right)} + { }g_{m3\left( 8 \right)} } \right) \times V_{X + \left( - \right)} + \left( {g_{m2\left( 5 \right)} + { }g_{m4\left( 7 \right)} } \right) \times V_{Y - \left( + \right)} } \right)}}{{\frac{1}{{r_{{o9\left( {10} \right)}} }} + \left( {g_{m1\left( 6 \right)} + { }g_{m3\left( 8 \right)} } \right) + \left( {g_{m2\left( 5 \right)} + { }g_{m4\left( 7 \right)} } \right)}}} \hfill \\ \end{array}$$

(8)

using (7) and (8), small signal voltage and internal resistance at node B(C) can be written as Eq. (9) and (10):

$$V_{B\left( C \right)} = \left( {i_{ac1\left( 2 \right)} + i_{ac5\left( 6 \right)} } \right)R_{outB\left( C \right)} = R_{outB\left( C \right)} { }\left( {V_{x + \left( - \right)} { }A_{1\left( 2 \right)} - { }V_{x - \left( + \right)} { }A_{3\left( 4 \right)} + V_{y - \left( + \right)} { }A_{5\left( 6 \right)} - { }V_{y + \left( - \right)} { }A_{7\left( 8 \right)} } \right)$$

(9)

$$R_{outB\left( C \right)} = { }r_{{o25\left( {26} \right)}} { }//\,r_{{o9\left( {10} \right)}} { }g_{{m1\left( 6 \right){ }}} r_{o1\left( 6 \right)} { }//r_{o10\left( 9 \right)} { }g_{{m5\left( 2 \right){ }}} r_{o5\left( 2 \right)} \cong { }r_{{o25\left( {26} \right)}}$$

(10)

where A_is can be derived based on Eq. (1) and (2) as follow:

$$\begin{array}{*{20}l} {A_{1\left( 2 \right)} } \hfill & { = g_{m1\left( 6 \right)} - { }g_{m1\left( 6 \right)} r_{{o9\left( {10} \right)}} \frac{{g_{m1\left( 6 \right)} + g_{m3\left( 8 \right)} }}{{ - 1 + r_{{o9\left( {10} \right)}} \left( {g_{m1\left( 6 \right)} + g_{m2\left( 5 \right)} + g_{m3\left( 8 \right)} + g_{m4\left( 7 \right)} } \right)}}} \hfill \\ {A_{3\left( 4 \right)} } \hfill & { = g_{m5\left( 2 \right)} r_{o10\left( 9 \right)} \frac{{g_{m6\left( 1 \right)} + g_{m8\left( 3 \right)} }}{{ - 1 + r_{o10\left( 9 \right)} \left( {g_{m5\left( 2 \right)} + g_{m6\left( 1 \right)} + g_{m7\left( 4 \right)} + g_{m8\left( 3 \right)} } \right)}}} \hfill \\ {A_{5\left( 6 \right)} } \hfill & { = g_{m5\left( 2 \right)} - { }g_{m5\left( 2 \right)} r_{o10\left( 9 \right)} \frac{{g_{m5\left( 2 \right)} + g_{m7\left( 4 \right)} }}{{ - 1 + r_{o10\left( 9 \right)} \left( {g_{m5\left( 2 \right)} + g_{m6\left( 1 \right)} + g_{m7\left( 4 \right)} + g_{m8\left( 3 \right)} } \right)}}} \hfill \\ {A_{7\left( 8 \right)} } \hfill & { = g_{m1\left( 6 \right)} r_{{o9\left( {10} \right)}} \frac{{g_{m2\left( 5 \right)} + g_{m4\left( 7 \right)} }}{{ - 1 + r_{{o9\left( {10} \right)}} \left( {g_{m1\left( 6 \right)} + g_{m2\left( 5 \right)} + g_{m3\left( 8 \right)} + g_{m4\left( 7 \right)} } \right)}} } \hfill \\ \end{array}$$

(11)

When differential voltage signal is applied to the input nodes (Y₊, Y_-), as $V_{gs1} = V_{gs3} ,{ }V_{gs2} = V_{gs4} ,{ }V_{gs5} = V_{gs7} ,{ }V_{gs6} = V_{gs8}$ and M₁-M₈ have the same bias current, we can assume that ${ }g_{m1} = g_{m3} ,g_{m2} = g_{m4} ,g_{m5} = g_{m7} ,g_{m6} = g_{m8}$. In addition, in the denominator of Eq. (11) $r_{{o9\left( {10} \right)}} \left( {g_{m1\left( 6 \right)} + g_{m2\left( 5 \right)} + g_{m3\left( 8 \right)} + g_{m4\left( 7 \right)} } \right) \gg - 1$. As a result, A₁-A₈ can be expressed as Eq. (12) and $V_{B\left( C \right)}$ can be simplified to Eq. (13). On the other hand, when a common-mode voltage is applied to the input nodes (terminals Y) since the bias currents of M1–M8 are not equal anymore, A₁-A₈ are defined as previously shown in Eq. (11).

$$A_{1} = A_{4} = A_{6} = A_{7} = \frac{{g_{m1} \times g_{m2} }}{{g_{m1} + g_{m2} }},\,A_{2} = A_{3} = A_{5} = A_{8} = \frac{{g_{m5} \times g_{m6} }}{{g_{m5} + g_{m6} }}$$

(12)

$$V_{B\left( C \right)} = R_{outB\left( C \right)} { }\frac{{g_{m1\left( 5 \right)} \times g_{m2\left( 6 \right)} }}{{g_{m1\left( 5 \right)} + g_{m2\left( 6 \right)} }}\left( {\left( {V_{x + \left( - \right)} { } - { }V_{x - \left( + \right)} } \right) - \left( {V_{y + \left( - \right)} - { }V_{y - \left( + \right)} } \right)} \right)$$

(13)

The drain voltage and internal resistance of M₁₁(M₁₂) are shown in Eq. (14) and (15), respectively. Using Eq. (14) and KCL at X₊ (X_-), voltage at X₊ (X_-) node is as Eq. (16).

$$V_{{d,M11\left( {12} \right)}} = - i_{{ac27\left( {28} \right)}} R_{{outdM11\left( {12} \right)}} = - g_{{m27\left( {28} \right)}} .R_{{outd,M11\left( {12} \right)}} .V_{B\left( C \right)}$$

(14)

$$R_{{outdM11\left( {12} \right)}} = r_{{o27\left( {28} \right)}} //r_{{o11\left( {12} \right)}}$$

(15)

$$V_{x + \left( - \right)} = { }V_{{dM11\left( {12} \right)}} { }\frac{{g_{{m21\left( {22} \right){ }r_{{o14\left( {15} \right)}} }} }}{{\left( {g_{{m21\left( {22} \right)}} r_{{o14\left( {15} \right)}} + g_{{m31\left( {32} \right)}} + r_{{o14\left( {15} \right)}} + 1} \right)}}$$

(16)

Based on Eq. (1) to (10), voltage at terminal X is simplified as follow:

$$V_{x + \left( - \right)} = A_{{9\left( {10} \right)}} { }A_{1\left( 2 \right)} \left( {\left( {V_{x + \left( - \right)} { } - { }V_{x - \left( + \right)} } \right) - (V_{y + \left( - \right)} - { }V_{y - \left( + \right)} ){ }} \right)$$

(17)

where,

$$A_{{9\left( {10} \right)}} = - g_{{m27\left( {28} \right)}} .\left( {r_{{o27\left( {28} \right)}} //r_{{o11\left( {12} \right)}} } \right){ } \times \frac{{g_{{m21\left( {22} \right){ }r_{{o14\left( {15} \right)}} }} \times r_{{o25\left( {26} \right)}} }}{{\left( {g_{{m21\left( {22} \right)}} r_{{o14\left( {15} \right)}} + g_{{m31\left( {32} \right)}} + r_{{o14\left( {15} \right)}} + 1} \right)}}$$

For differential-mode voltage signals ($V_{Y + } = - V_{Y - } = \frac{{V_{Ydiff} }}{2}{ }$), based on Eq. (18), we get:

$$V_{x + } - { }V_{x - } = V_{xdiff} = V_{Ydiff} \left( {\beta_{4} - \frac{{\beta_{2} \beta_{3} }}{{2\beta_{1} }}} \right)$$

(18)

As a result, the differential gain between X and Y is as follow in Eq. (19).

$$Av_{XYdiff} = \frac{{V_{Xdiff} }}{{V_{Ydiff} }} = \beta_{4} - \frac{{\beta_{2} \beta_{3} }}{{2\beta_{1} }}$$

(19)

Where,

$$\beta_{1} = 1 - A_{1} A_{9} - A_{2} A_{10} \cong - \left( {A_{1} A_{9} + A_{2} A_{10} } \right) = - \frac{{ + A_{10} \left( {g_{m5} g_{m6} \left( {g_{m1} + g_{m2} } \right)} \right)}}{{\left( {g_{m1} + g_{m2} } \right) \times \left( {g_{m5} + g_{m6} } \right)}}$$

$$\beta_{4} = \frac{{A_{1} + A_{2} }}{{2A_{2} }} = \frac{{g_{m1} g_{m2} \left( {g_{m5} + g_{m6} } \right) + g_{m5} g_{m6} \left( {g_{m1} + g_{m2} } \right)}}{{2\left( {g_{m5} g_{m6} \left( {g_{m1} + g_{m2} } \right)} \right)}}$$

On the other hand, According to Eq. (18) , for common-mode voltage signals (V_Y+  = V_Y- = V_Ycom) we have:

$$V_{x + } = { }V_{x - } = V_{xcom} = V_{Ycom} \times \left( {\beta_{6} - \frac{{\beta_{5} \beta_{7} }}{{\beta_{1} }}} \right)$$

(20)

and therefore, the common-mode gain between X and Y can be derived as follows:

$$Av_{XYcom} = \frac{{V_{Xcom} }}{{V_{Ycom} }} = \beta_{6} - \frac{{\beta_{5} \beta_{7} }}{{\beta_{1} }}$$

(21)

where,

$$\beta_{5} = A_{3} A_{9} \left( {A_{6} - A_{8} } \right) + \left( {A_{5} - A_{7} } \right)\left( {1 - A_{2} A_{10} } \right)$$

$$\beta_{6} = \frac{{A_{5} - A_{7} }}{{A_{3} A_{9} }}$$

$$\beta_{7} = \frac{{A_{3} A_{9} - A_{1} A_{9} + 1}}{{A_{3} A_{9} }} \cong \frac{{A_{3} - A_{1} }}{{A_{3} }}$$

1.2 Current Gain between X and Z terminals

The internal resistance of X nodes can be derived as:

$$r_{x + \left( - \right)} \cong \frac{1}{{g_{{m{\text{MT}}1\left( 3 \right) + }} g_{{m{\text{MT}}5\left( 7 \right)}} }}$$

(22)

For current input signals, the output current signal at Z terminals are as follow:

$$i_{Z + \left( - \right)} = \alpha_{1\left( 2 \right)} { }i_{X + \left( - \right)} \to i_{Z + \left( - \right)} = { }\frac{{V_{Z + \left( - \right)} }}{{R_{L} }} = { }\alpha_{1\left( 2 \right)} { }\frac{{V_{X + \left( - \right)} }}{{R_{ext} //r_{x + } }}{ } \to \frac{{V_{Z + \left( - \right)} }}{{V_{X + \left( - \right)} }} = { }\frac{{\alpha_{1\left( 2 \right)} R_{L} }}{{R_{ext} //r_{x + } }}$$

(23)

Where,

$$\alpha_{1\left( 2 \right)} = { }\frac{{i_{{M31\left( {32} \right)}} }}{{i_{{M33\left( {34} \right)}} }} = { }\frac{{\left( {V_{{gs31\left( {32} \right)}} - V_{{Th31\left( {32} \right)}} } \right)}}{{\left( {V_{{gs31\left( {32} \right)}} - V_{{Th33\left( {34} \right)}} } \right)}} \times \frac{{1 + \lambda { }\frac{{V_{X + \left( - \right)} }}{{g_{{m21\left( {22} \right)}} r_{{o21\left( {22} \right)}} }}}}{{1 + \lambda { }V_{Z + \left( - \right)} }}$$

For differential mode current signals, ignoring the channel-length modulation effect $\left( \lambda \right)$, the current gain between Z and X terminals can be expressed as follow:

$$i_{Zdiff} = i_{Z + } - i_{Z - } = { }V_{X + } { }\left( {\frac{{\alpha_{1} }}{{R_{ext} //r_{x + } }}{ }} \right){ } - V_{X - } { }\left( {\frac{{\alpha_{2} }}{{R_{ext} //r_{x - } }}{ }} \right) = V_{X + } { } \times \beta_{7} + \frac{{\beta_{4} \alpha_{2} }}{{R_{ext} //r_{x - } }}V_{ydiff}$$

(24)

According to Eq. (18) and (19), we have:

$$V_{X + } = \frac{{V_{xdiff} - \beta_{4} }}{{\beta_{3} }},\,V_{ydiff} = \frac{{V_{xdiff} }}{{Av_{XYdiff} }}$$

(25)

Assuming that $r_{x + } = r_{x - } = r_{x}$ and, as a result $V_{xdiff} = r_{x} { }i_{xdiff}$, and using Eq. 24)ifferential current Z terminal can be calculated by Eq. (26) as follow.

$$i_{Zdiff} = i_{Xdiff} \left( {r_{x} { }\left( {\beta_{7} { }\frac{{Av_{XYdiff} - \beta_{4} }}{{\beta_{3} { }Av_{XYdiff} }} + { }\frac{{\beta_{{4{ }}} \alpha_{2} }}{{{ }Av_{XYdiff} { }\left( {r_{x} } \right)}}} \right)} \right)$$

(26)

Therefore, the differential current gain between X and Z nodes can now be expressed as given in Eq. (27).

$$Ai_{ZXdiff} = \frac{{i_{Zdiff} }}{{i_{Xdiff} }} = { }r_{x} { }\left( {\beta_{7} { }\frac{{Av_{XYdiff} - \beta_{4} }}{{\beta_{3} { }Av_{XYdiff} }} + { }\frac{{\beta_{{4{ }}} \alpha_{2} }}{{{ }Av_{XYdiff} { }\left( {R_{ext} + r_{x} } \right)}}} \right)$$

(27)

Where,

$$\beta_{7} = \frac{{\alpha_{1} }}{{R_{ext} //r_{x + } }} + \frac{{\alpha_{2} \left( {1 - A_{1} A_{9} } \right)}}{{A_{3} A_{9} { }(R_{ext} //r_{x - } )}}$$

Moreover, the differential voltage gain between Y and Z nodes can be calculated by Eq. (28) as follows:

$$Av_{ZYdiff} = \frac{{V_{zdiff} }}{{V_{Ydiff} }} = \frac{{i_{Zdiff} { }R_{L} }}{{\left( {\frac{{r_{x} i_{Xdiff} }}{{Av_{XYdiff} }}} \right)}} = \frac{{R_{L} }}{{r_{x} }} \times Av_{XYdiff} \times Ai_{{ZXdiff{ }}}$$

(28)

For common-mode current signals (V_Y+  = V_Y- = V_Ycom), the common-mode current signal at Z terminals are given by Eq. (29).

$$i_{Zcom} = { }V_{X + com} { }\left( {\frac{{\alpha_{1} }}{{2R_{ext} //r_{x + } }}{ }} \right) - { }V_{X - com} { }\left( {\frac{{\alpha_{2} }}{{2R_{ext} //r_{x - } }}{ }} \right){ }$$

(29)

Assuming $r_{x + } = r_{x - } = r_{x} { },{ }r_{x} \ll { }2R_{ext} {\text{ and as }}V_{xcom} = r_{x} { }i_{xcom}$, then froEq. (11a), we obtain:

$$\left( {\beta_{8} - \beta_{9} } \right) , V_{Ycom} = \left( {\beta_{8} - \beta_{9} } \right)\frac{{r_{x} { }i_{xcom} }}{{Av_{XYcom} }}{ }$$

(30)

As a result, the common-mode current and voltage gains between X and Z nodes can be derived as given in Eq. (31) and Eq. (32), respectively.

$$Ai_{ZXcom} = \frac{{i_{Zcom} }}{{i_{Xcom} }} = \frac{{\left( {\beta_{8} - \beta_{9} } \right)r_{x} }}{{Av_{XYcom} }}$$

(31)

$$i_{Zcom} = \frac{{V_{Zcom} }}{{R_{L} }} = \left( {\beta_{9} } \right)V_{Ycom} { } \to Av_{ZYcom} = \frac{{V_{Zcom} }}{{V_{Ycom} }} = R_{L} \left( {\beta_{8} - \beta_{9} } \right)$$

(32)

Where,

$$\beta_{8} = \frac{{\alpha_{1} }}{{2R_{ext} //r_{x + } }} \times \left( {\frac{{(A_{6} - A_{8} )A_{3} A_{9} A_{10} - \left( {A_{9} A_{5} - A_{9} A_{7} } \right)\left( {1 - A_{2} A_{10} } \right)}}{{A_{3} A_{9} - \left( {1 - A_{2} A_{10} } \right)\left( {1 - A_{1} A_{9} } \right)}}} \right)$$

$$\beta_{9} = { }\frac{{\left( {A_{9} A_{5} - A_{9} A_{7} } \right)A_{4} A_{10} - (A_{6} A_{10} - A_{8} A_{10} )\left( {1 - A_{1} A_{9} } \right)}}{{A_{4} A_{10} \left( {A_{3} A_{9} - \left( {1 - A_{2} A_{10} } \right)\left( {1 - A_{1} A_{9} } \right)} \right)}}$$

1.3 Voltage and CurrenCMRR

By combining Eq. (19) and (21), voltage CMRR between X and Y terminals is obtained as given in Eq. (27), (30)

$$CMRR_{{V_{XY} }} = \frac{{Av_{XYdiff} }}{{Av_{XYcom} }} = { }\frac{{\beta_{4} - \frac{{\beta_{2} \beta_{3} }}{{2\beta_{1} }}}}{{\beta_{6} - \frac{{\beta_{5} \beta_{7} }}{{\beta_{1} }}}}$$

(33)

Using (28) and (31), voltage CMRR between terminals Z and Y can be expressed by Eq. (34) as follows.

$$CMRR_{{V_{ZY} }} = \frac{{Av_{ZYdiff} }}{{Av_{ZYcom} }} = { }\frac{{{ }\beta_{7} \left( {CMRR_{{V_{XY} }} \times \left( {\beta_{6} - \frac{{\beta_{5} \beta_{7} }}{{\beta_{1} }}} \right) - \beta_{4} } \right)\left( {R_{ext} + r_{x} } \right) + \beta_{3} \beta_{{4{ }}} \alpha_{2} { })}}{{\beta_{3} \left( {\beta_{8} - \beta_{9} } \right)\left( {R_{ext} + r_{x} } \right)}}$$

(34)

Finally using Eq. (27) and (31), current CMRR between Z and X terminals can be simplified to Eq. (35).

$$CMRR_{{I_{ZX} }} = \frac{{Ai_{ZXdiff} }}{{Ai_{ZXcom} }} = \frac{{\left( {\beta_{7} \left( {\left( {CMRR_{{V_{XY} }} \times \beta_{6} - \frac{{\beta_{5} \beta_{7} }}{{\beta_{1} }}} \right) - \beta_{4} } \right)\left( {R_{ext} + r_{x} } \right) + { }\beta_{3} \beta_{{4{ }}} \alpha_{2} } \right) \times \left( {\beta_{6} - \frac{{\beta_{5} \beta_{7} }}{{\beta_{1} }}} \right)}}{{\left( {CMRR_{{V_{XY} }} \times \beta_{6} - \frac{{\beta_{5} \beta_{7} }}{{\beta_{1} }}} \right) \times \beta_{3} \left( {\beta_{8} - \beta_{9} } \right) \times \left( {R_{ext} + r_{x} } \right)}}$$

(35)