1 Introduction

In recent years, the inversion technique using the multilevel configuration known as Multilevel Inverters (MLI) has been widely adopted due to its low Total Harmonic Distortion (THD) at a low switching frequency, a critical characteristic for grid synchronization of Photo Voltaic (PV) power plants. MLI's concept is based on the production of stepped output voltage and is approximated to a sinusoidal voltage with an increase in the number of steps. The stepped response is obtained by an ensemble of properly placed power electronic devices with switching either isolated DC sources [1] or multiple DC sources obtained through spilt capacitors by diode clamping [2] otherwise by flying capacitors [3]. Apart from lower THD, MLI rises above the restrictions due to the limited rating of power semiconductors, reduces \(\frac{dV}{{dt}}\) stress of switch and issues due to common voltage [4, 5]. The International standards allow direct grid connection of MLI for medium and high power applications without isolation [5], thus providing a viable option for a filter-less and transformerless system. The adoption of this system reduces the losses, space and cost. These advantages can be realized provided the following challenges are resolved:

  • The increase in controlled switches reduces the THD thereby, increasing the control complexity and cost in terms of requirements in driver circuits.

  • The PV system is designed for long durations; however, the low-reliability power electronic devices reduce the converter's reliability.

The control complexity challenge due to numerous switches is solved by developing the Reduced Part Count MLI (RPC-MLI). The adoption of RPC-MLI for PV systems requires a careful study of the PWM technique to reduce the THD content, a proper control algorithm for grid integration and a fault detection algorithm. Both PWM techniques and power control algorithms for grid integrations have been vastly studied [6,7,8]. A survey in [9, 10] concluded that power electronic switches are more susceptible to failure in any system. These faults play a vital role as the number of high powered grid integrated PV plants increases. The fault of switches in a power electronic converter can hinder the plant operation and without a proper algorithm to address the reliability a huge block of power is suddenly removed from the grid. These faults in switches may cause many issues related to the grid's stability as a massive portion of power is suddenly unavailable. The converters along with control algorithms that mitigates these issues in smart grid are coined as smart converters in [11]. The algorithms associated with increasing the converter reliability are often defined as Fault Detection and Isolation (FDI) algorithms.

The Fault Detection and Isolation (FDI) scheme is defined in [12] as “a monitoring system that is used to detect faults and diagnose their location and significance in a system.” Various methodologies adopted in literature for FDI schemes such as the Quantitative approach, Qualitative approach and soft computing approach have been discussed in [13]. The implementation of the FDI scheme increases the reliability of a Cascaded H-Bridge MLI (CHBMLI) from 86 to 99% [14] and usage of Reduced Part Count (RPC) MLI reduces the complexity of the circuit [15]. This paper concentrates on the development of the FDI scheme to RPC- MLI. In literature, FDI scheme is mostly implemented using soft computing techniques such as a neural network to classify faults. The [16] discusses the FDI scheme by placing the sensors to sensors output voltage and current at each bridge. Even though methodology is simple for execution an extra cost is incurred for the sensors. In literature the FDI scheme has been based on either rule based method or soft computing base method. In [17] a FDI scheme based on the mean voltages at each bridge has been studied. In [18, 19], a combination of soft computing technique and a simplified rule based algorithm is adopted to detect an open-circuit fault in switches for symmetric operation of CHB-MLI. [20] proposes an optimization based neural network for development of FDI scheme for CHBMLI. In [21] an neural network based FDI scheme has been discussed for the asymmetric operation of CHBMLI. The researchers have also tried to solve the issue of reliability of modification in the topology. In [22] an additional cross coupled CHB MLI unit is incorporated in CHBMLI to increase the reliability. The increase in reliability also causes increase in cost. [23] proposes a fault tolerant MLI that includes an redundant leg consisting of 6 switches. This redundancy increases with the increase in the number of levels.

Based on the literature survey carried for the isolation of faulty switches in the circuit, the following are necessary conditions to be satisfied.

  • There must be a closed-loop path in the circuit after isolation of fault.

  • A closed-loop is not formed in certain circuits when specific switches under fault conditions, such switches are referred to as critical switches. A redundant switch is required to replace the faulty switch and such switches are termed as critical switches in this study.

  • The economic consideration dictates the critical switches to be less.

  • In a few cases, additional switches are also utilized to isolate the faulty switch [24].

The selection of a proper RPC-MLI for the issue of reliability requires satisfaction of the above conditions. In Ref. [25], a cascaded connection of half-bridge circuits is connected to a full-bridge inverter termed as Polarity Changer (PC) to produce an alternating waveform from the unidirectional output. This circuit has ‘m + 3′ switches where ‘m’ represents number of levels. The circuit consists of 8 switches for 5 level output with six critical switches, of which four are in PC and one in each cascaded half-bridge. thus requiring redundancy, increasing with the number of switches. In Ref. [26] a 5 level unidirectional staircase waveform is produced by a circuit similar to a bridge circuit where the load is replaced by switch and DC sources replace two diagonal switches. An alternating waveform is obtained by a PC similar to 15. A Switch is placed for the freewheeling action of PC. This circuit has ‘m + 3′ switches where ‘m’ represents number of levels.

The circuit has eight switches for five-level output; six are critical switches; therefore, redundant switches are required in the circuit, which increases with the number of levels. Ref. [27] Utilizes two dc sources with two unidirectional and two bidirectional switches to generate a positive staircase waveform. This circuit is connected to a PC similar to Ref. [25]. A switch is placed for the freewheeling action of PC. This circuit has \(\frac{{3\left( {m + 5} \right)}}{2}\) switches where ‘m’ represents number of levels. The circuit has eight switches, of which two are bidirectional for five-level output, and all of them are critical switches, so there must be redundant switches placed in the circuit. This redundancy increases with an increase in levels. Ref. [28] utilizes six switches and two DC sources for five-level operations. In this circuit, all the switches are critical, but if there is a fault in switching, then the DC source could be bypassed using another switch that was dormant until fault occurrences. This solution fails when two adjacent switches are under fault conditions. This circuit has \(\frac{{3\left( {m - 1} \right)}}{2}\) switches where ‘m’ represents number of levels. Ref. [29] utilizes 2 DC source six switches and eight diodes for five-level operations. In this circuit, switches along with all the diodes are critical and require redundancy. This circuit has \(\frac{{3\left( {m - 1} \right)}}{2}\) switches where ‘m’ represents number of levels. Ref. [30] utilizes two DC source and six switches for five-level operation. In this circuit, all are critical switches, so when a fault occurs in these switches, an alternate circuit is not possible, so there must be redundant switches placed in the circuit.

Based on the survey provided, a conclusion is derived that the number of critical switches are increasing with increase in the level. This requires a high cost as the system requires many redundancies and the control circuit becomes more complicated. Therefore, development of a RPC-MLI with reduced critical number of switches is a priority to develop a transformerless and filter-less PV grid system. This paper proposes a modified form of Cascaded Half-Bridge MLI with Polarity Changer (PC) from Ref. [25]. As the proposed system requires only unidirectional converter the switch present in lower part of the half bride is replaced by diode. This reduces the requirement of high cost controlled critical switches.

This circuit has an inherent capability of fault isolation of switches in the cascaded half-bridge, that has been validated through simulation and experimentation. The circuit consists of 5 critical switches irrespective of the number of levels, thereby reducing the cost for redundancy with respect to CHBMLI and RPC-MLI circuits. The system is designed and simulated for a three-phase system with PV as an input. The article concentrates only on the open circuit faults of switches in the proposed converter, which are difficult to trace than short circuit faults. Since the redundant switches must be incorporated in the switching circuit during an open-circuit fault in switches and the isolated switches are to be restored, a fault detection algorithm is proposed for modified MLI. Therefore, the contributions of the article can be summarized as follows:

  • Proposes a Modified Cascaded Half Bridge MLI with Polarity Changer (MChBMLI with PC) that has higher reliability and less complexity as the total number of controlled switches are less compared to other RPC-MLI.

  • Adoption of Gravitational Search Algorithm (GSA) for solving of Selective Harmonic Elimination (SHE)

  • Development of rule based FDI algorithm based on multi resolution analysis for detection of open circuit faults in switches for proposed circuit.

The article is organized into seven sections. The Sec-2 describes the symmetric operation mode of the proposed Modified Cascaded Half-Bridge MLI with PC. The Sec-3 describes the design of the topology, and the Sec-4 provides the simulation results for both three phase and single phase. The simulations are carried for both three phase and single phase system. This section provides results for irradiance of 1000 W/m2 and temperature 25 °C. A simulation study is carried by creation of open circuit faults. Based on the inferences from the results of Sec-4, a Fault Detection algorithm is developed in Sec-5. The Sec-6 validates the algorithm with experimental results obtained from the laboratory. The Sec-7 provides a comparative analysis of proposed MLI with MLI present in literature. A conclusion to the article is provided in sec-8.

2 System description

The grid connected PV system requires tracking of maximum power point and a grid integration algorithm. The maximum power point operation is generally obtained by two methodologies. In the first methodology incorporating the MPPT algorithm in the grid integration as described in [31].The second method is to adopt the conventional methodology of utilizing a DC-DC converter for MPPT algorithm as in [31]. The present work adopts the tracking of maximum power point through DC-DC converter as shown in Fig. 1. The three phase PV system consist of three blocks that produces an alternating voltage for each phase. The control algorithm for grid integration provides modulation index for PWM Technique.

Fig. 1
figure 1

Block diagram representing the system

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The cascaded half bridge MLI with PC is shown in Fig. 3a. The proposed Modified Cascaded Half-Bridge MLI with PC consist of three DC supplies, eight switches and three diodes for a seven-level operation is shown in Fig. 2b. The proposed circuit is obtained by replacing the bidirectional switches in the half bridge (S1,S’1,S2 S’2,S3 and S’3) in Fig. 2a with unidirectional switches and diodes as shown in Fig. 3b. A freewheeling switch ‘F’ is placed for the freewheeling of inductor current. The modifications in the topology of Fig. 3a limits its usage only for unidirectional applications and cannot function properly loads with for very low power factors. As the PV grid system is a unidirectional load and the IEEE standards dictates the operation has to near unity power factor the proposed converter suits appropriately despite of its limitations. The incorporated modifications has removed the critical switches in Fig. 2a (S’1,S’2, and S’3) that increase with increase in level. In the proposed converter the increase in level is obtained by incorporating aa DC source is parallel with combination of non-critical switch in series with diode.

Fig. 2
figure 2

a circuit diagram of Cascaded Half Bridge MLI with Polarity Changer b Circuit diagram of Modified cascaded half-bridge MLI with PC for seven levels c Flow of current in the circuit during + V1 d Flow of current during + (V1 + V2) e Flow of current during + (V1 + V2 + V3) f Flow of current during 0 V and the current flowing through Diodes of P1 and P3 g Flow of current in the circuit during 0 V and the current flowing through diodes of P2 and P4

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Fig. 3
figure 3

Graph of number of switches vs. number of levels for circuits of [25,26,27,28,29,30]

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The cascaded connection of modified half-bridge circuits provides a positive voltage waveform with a staircase shape. A Polarity Changer (PC) interpreted as a full-bridge inverter is utilized to produce an alternating waveform along with a switch F that provides a freewheeling action for any load without a unity power factor. The switches S1, S2 and S3 have controlled switches of each half-bridge, respectively. When the switches S1, S2 and S3 are on, the Diodes D1, D2 and D3 are in reverse bias. This article concentrates on the symmetric mode of operation.

In the symmetric mode of operation, the DC Voltage sources have the same voltage (V1 = V2 = V3 = V); thus, the maximum number of steps obtained is seven viz., + 3 V, + 2 V, + V, 0, –V, –2 V and –3 V. The voltage + V1 is obtained when switches S1, P1 and P3 are turned on. During this state the diodes D2 and D3 are forward bias while the Diode D1 is reverse biased as switch S1 is on as shown in Fig. 2b. Similarly, voltages + V2 and + V3 is obtained when switches S2, S1 are on and switches S1, S2 and S3 are on respectively with P1 and P3 in on condition as shown in Fig. 2c, d.

The negative polarity of output voltage is obtained with same switching while in Polarity Changer switches P2 and P4 are on. At the end of the positive cycle, even though switches P2 and P4 are provided with gating signals, the current in RL load prevents the switches from turning on and the current finds the path of body diodes of P1 and P3 through switch F, as shown in Fig. 2e. Figure 2e, f represent the current flow when an RL load is connected and the inductor is discharged during 0 V. Similarly, during the end of the negative cycle, the current travels through the body diodes of P2 and P4. The switching table for the symmetric operation of the proposed circuit is shown in Table 1. The total number of controlled switches in the circuit is \(\left( {\frac{m + 9}{2}} \right)\) where ‘m’ is number of levels and is an odd number greater than two. This is the least number of switches compared to circuits in discussed in Sec-1, represented in a graph shown in Fig. 3.

Table. 1 Switching table for the symmetric mode of operation for proposed circuit (seven-level operation)
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3 Design of modified cascaded half-bridge mli with polarity changer

The design of a system consisting of modified MLI, load and PV system is described in this section. The design is carried out with considerations of PV power plants. A Soltech 1STH-250WH has been selected for simulation purpose. The power-voltage characteristics of the panel for different irradiance and temperature is shown in Fig. 4a, b respectively. The maximum open circuit voltage (Voc) is kept at 37.3 V and short circuit current (Isc) is considered 8.45 A for each panel for the experimental purpose. The voltage at maximum power for PV panel as per the changes of temperature and irradiance is shown in Table 2.

Fig. 4
figure 4

Solar module PV characteristics for Soltech 1 STH-250 W a various irradiance at 25 °C b various temperature for 1000 W/m2 irradiance

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Table 2 Change in voltage as per irradiance and temperature
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The proposed modified multilevel inverter involves selecting switching angles, selecting switch ratings, and designing a snubber circuit. The switching angles are selected by the SHE method. The equations defining fundamental components and harmonic components are found by applying Fourier transform on output waveform and are shown in Eqs. 1, 2, and 3 for seven level and Eqs. 4, 5, 6, and 7 for nine level.

For seven-level

$$\cos \theta_{1} + \cos \theta_{2} + \cos \theta_{3} = 3M$$
(1)
$$cos3\theta_{1} + \cos 3\theta_{2} + \cos 3\theta_{3} = 0$$
(2)
$$cos5\theta_{1} + \cos 5\theta_{2} + \cos 5\theta_{3} = 0$$
(3)

For nine-level

$$\cos \theta_{1} + \cos \theta_{2} + \cos \theta_{3} + \cos \theta_{4} = 4M$$
(4)
$$cos3\theta_{1} + \cos 3\theta_{2} + \cos 3\theta_{3} + \cos 3\theta_{4} = 0$$
(5)
$$cos5\theta_{1} + \cos 5\theta_{2} + \cos 5\theta_{3} + \cos 5\theta_{4} = 0$$
(6)
$$cos7\theta_{1} + \cos 7\theta_{2} + \cos 7\theta_{3} + \cos 7\theta_{4} = 0$$
(7)

where.

M-Modulating index in per unit.

θ1, θ2 θ3 and θ4-switching angle for each bridge.

The Eqs. 1, 2, and 3 and 4, 5, 6 and 7 are transcendental equations that are solved by using GSA adopted in [32], providing a solution as θ1 = 10.41°, θ2 = 30.32° and θ3 = 53.02°. Equation (8) represents the condition to be satisfied for the current to reach zero during the zero voltage level.

$$\theta_{1} > \tan^{ - 1} (\frac{\omega L}{R})$$
(8)

The load for design purposes is taken as predominantly resistive RL load as the IEEE STD 1547/UL 1741 states that the inverter circuit operates at unity power factor. The required reactive power and voltage control are obtained by installing a reactive power compensation system (RCS), generally an SVC or STATCOM. Thus the load has R = 100 ohms and L = 25 mH, which gives a power factor of 0.94 lagging. This design also satisfies condition as \({\text{tan}}^{ - 1} \left( {\frac{\omega L}{R}} \right)\) is 8.93° < 10.41°.

The switches' ratings mainly consist of determination of peak voltage across switch and peak current through the switch. For the given circuit, the maximum current through the switches I max is 10.8 A, and the maximum voltage across switch at steady state is Vmax is 108 V. Thus, the switch selected by the above ratings is IRL650, whose voltage across the drain to source is (Vds) 200 V and drain current is (Id) 19 A. IN4007 diode is selected.

Based on the parameters obtained from the datasheet, the RC snubber circuit is designed, and the obtained values for a damping factor of 0.65 are snubber inductance Ls = 0.6 mH and snubber capacitor is Cs = 585 uF with snubber resistance Rs = 41.6 Ohms. The snubber inductance is neglected as the load inductance is much higher.

4 Simulation results

The simulation study has been carried for both nine and seven level. A nine-level MLI is studied as the grid integration requires THD less than 8% for system voltage less than 1 kV as per IEEE STD- 519 2014. A seven-level MLI has been implemented for development of FDI algorithm. The system is implemented in simulated in MATLAB-Simulink environment. The MPPT of the PV is obtained by employing Petrub and Observe (P&O) algorithm. The PV terminal voltage, current and the power are shown in Fig. 5. The time taken for settling at the steady state is 2 seconds. The output voltage is then provided to the proposed converter and the output voltage and current is shown in Fig. 6. The output voltage and current is provided for an R load as it replicates the response of grid. The nine-level output voltage does not have a flat voltage as the terminal voltage of the PV is not constant. This ripple can be reduced by employing advance MPPT algorithms and maintaining the capacitor voltage of the DC-DC converter. The THD in terms of percentage for the nine-level operation of the converter is shown in Fig. 7. The THD for nine level proposed MLI with GSA based SHE with MPPT algorithm is shown in Fig. 7a. The lack of stiff voltage across capacitor causes certain asymmetry in the waveform that is reflected in THD. A nine-level MLI with DC source of 100 V is also studied. The output voltage along with THD is shown in Fig. 7b.

Fig. 5
figure 5

Current, voltage and power of photo voltaic panel for maximum power point tracking

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Fig.6
figure 6

Simulation circuit of seven-level modified cascaded half-bridge MLI with PC

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Fig.7
figure 7

Percentage THD of nine-level proposed converter a with MPPT algorithm b with DC voltage source of 100 V

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The observed THD in both cases less than 8% and indiviual THD is less than 5%, therefore in compliance with IEEE STD-519 -2014 [33]. The analysis is also been carried for a seven level operation of the cproposed converter with a load current less than 1 A. The terminal voltage and current for various types of load for seven level operation is shown in Fig. 8. An observation can be made that the output voltage waveform remains same irrespective of the load.

Fig. 8
figure 8

Voltage and current waveforms of a R = 100 ohms b R = 10 ohms L = 25 mH

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An open circuit fault is created by removing the switch and the effects of these faults on output voltage are analyzed. The output voltage waveform for each switch fault is shown in a–f in Fig. 9. From the waveforms, it can be concluded that.

  • When either switch P1 or P3 is in fault conditions, then the waveform's symmetry is lost and the average voltage is positive as shown in Fig. 9b.

  • When either switch P2 or P4 is in fault conditions, then the waveform's symmetry is lost and the average voltage is negative as shown in Fig. 9c.

  • When switches S1, S2 and S3 are in an open circuit fault condition, then the output voltage waveform proves that fault isolation is an inherent characteristic of the proposed circuit as shown in Fig. 9d, e and f.

  • When the fault occurs in F, the output voltage waveform is distorted due to the lagging inductive current. Since the inverter is generally operated at the unity power factor, the stress across the switch is less than other switches; therefore, F's probability of fault is low and there is no effect of fault in F on the voltage waveform for unity power factor operation.

Fig. 9
figure 9

Output voltage waveform for an open circuit fault condition in a No Fault b Switch P1 or P3 or both c Switch P2 or P4 or both d Switch S1 e Switch S2 and f Switch S3 g Switch F

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5 Fault detection and isolation scheme

This circuit requires an FDI technique for its PC based on the above observations. Since the four switches present in the PC are critical to forming a closed-loop circuit, they are provided with redundancy. The fault detection technique employed for the switches in PC is based on the average output voltage. The switches P1 and P3 are named here as a positive group and switches P2 and P4 are termed as negative group switches. The formula for average voltage is given by

$$S = \frac{{\mathop \sum \nolimits_{i = 0}^{N} V_{oi} }}{N}{ }$$
(9)

when S is between −1 and 1 there is no fault in the PC. When S is greater than 1, the negative group switches are in fault condition given by a binary variable labelled ‘a.’ Similarly, when S is less than −1, the negative group switches are in fault condition given by a binary variable labelled ‘b.’ The non-critical switches should be detected so that troubleshooting is carried out. To detect the fault on the faulty switch Multi-Resolution Analysis (MRA) is carried out on the output voltage waveform as shown in Fig. 10. This is due to the fact that the load voltage does not vary with the change in loads. The mathematical representation of MRA is presented in [19] defined as

$$y_{ah} \left[ n \right] = \mathop \sum \limits_{k} h\left[ {k - 2n} \right]x\left[ k \right]$$
(10)
$$y_{al} \left[ n \right] = \mathop \sum \limits_{k} g\left[ {k - 2n} \right]x\left[ k \right]$$
(11)

where, yah[n] and yal[n] represent the output of high pass and low pass filters for signal x[k] respectively.

Fig.10
figure 10

Multi resolution analysis of voltage signal up to level-3

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The output voltage signals of the converter is subjected to MRA analysis and the output signals of low pass filter and high pass filter at level −1 is shown in Fig. 11. The open circuit faults in the MLI causes distortions in the output voltage waveforms. These distortions cause the changes in various harmonic components. In MRA the LPF and HPF are utilised to separate the low frequency components and high frequency components. The study of energy for these components can be correlated with the faults. The energy of the signal is calculated by adopting Parseval’s energy theorem shown by Eqs. (12), (13), where N is number of samples. Similarly, the energy of approximate coefficients and detailed coefficients of the third level is calculated for each open circuit fault for various irradiance and temperature. From the obtained data, it is observed that only the first approximate and detailed coefficients are sufficient to identify the fault. The energy levels E1 and E0 for various open circuit faults in switches at different irradiance and temperature are shown in Table 3.

$$E_{{level - 1 \left( {HFP} \right)}} = \mathop \sum \limits_{n = 1}^{N} y_{ah} \left[ n \right]$$
(12)
$$E_{{level - 1 \left( {LFP} \right)}} = \mathop \sum \limits_{n = 1}^{N} y_{al} \left[ n \right]$$
(13)
Fig.11
figure 11

Multi resolution analysis for output voltage with no fault condition at 1000 w/m2 and 25 °C

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Table 3 Energy levels for various open circuit fault
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The energy level No-Fault and open circuit fault of ‘F’ has overlapping values; thus, another energy level, E1, is taken for the classification of fault, which is tabulated in Table 4. Based on the obtained data, an algorithm is developed to detect the fault shown as a flowchart in Fig. 12. The output is represented in six variables [a b c d e f], which utilizes a binary system to differentiate between a fault and No-Fault condition. If any variable's value is one, then the system has an open circuit fault or else the value of the variable is 0. In this system, the representation of the variables is with respect to corresponding faults in switches is tabulated in Table 5. The algorithm has been developed based on four quantities defined as TF1, TF2, TF3 and TF4. These quantities obtained by considering the data on presented in Tables 4 and 5 as shown in Eqs. 14, 15, 16, and 17.

$$\rm Max\left( {E_{0} ~\;\rm for\;~\rm fault~\;in\;~\rm Switch\;~S_{1} } \right) < TF_{1} < \rm Min(E_{0} ~\rm for\;~\rm fault\;~\rm in~\;\rm Switch~\;S_{2} )$$
(14)
$$\rm Max\left( {E_{0} ~\;\rm for\;\rm fault\;~\rm in~\;\rm Switch~\;S_{2} } \right) < TF_{2} < \rm Min(E_{0} ~f\rm or\;\rm fault\;\rm in~\;\rm Switch~\;S_{3} )$$
(15)
$$\rm Max\left( {E_{0} ~for\;\rm fault\;\rm in\;\rm Switch\;S_{3} } \right) < TF_{3} < \rm Min(E_{0} ~\rm for\;No\;\rm fault\;\rm condition)$$
(16)
$$\rm Max\left( {E_{1} ~No\;\rm Fault\;\rm condition} \right) < TF_{4} < \rm Min(E_{1} ~\rm for\;\rm Fault\;\rm for\;F)$$
(17)
Table 4 Energy levels for various open circuit fault
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Fig. 12
figure 12

Flowchart for detection of open circuit fault in switches

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Table 5 Binary adaptation to represent a fault in switches
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The presented rule based FDI algorithm has output voltage as its input. The average of the voltage is initially checked to determine the conditions of switch in PC. The tolerance limit is kept between −1 to 1 to account for the asymmetry in waveform due to any transients during the operation. An MRA is done on the output voltage to find the approximate and detailed coefficients at level 3. Based on the energy levels and rules framed a decision is taken as shown in Table 6.

Table 6 Validation of fault detection algorithm from experimental results
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6 Experimentation and validation

A prototype of Modified cascaded MLI with PC has been developed in the laboratory with a DC source of supply of 30 V, as shown in Fig. 13a. The considered output load is a resistive as the inverter connected to the PV power plant operates with a unity power factor. The output voltage is measured through an Agilent DS-1002 DSO is depicted in Fig. 13b. The data shows the output voltage has a frequency of 49.5 Hz with an error of 1% in frequency as the system is designed for 50 Hz.This is, in turn connected to a PC a laptop. The output voltages are read by the PC and are subjected to the developed FDI algorithm. The experimental validation of FDI algorithm under various fault conditions is provided in Table 6. As the voltage level for the prototype is reduced compared to simulations the energy levels have also been altered. This alteration has caused the changes in the FDI scheme with respect to threshold values (TF1, TF2 TF3 and TF4) as shown in Fig. 12. The results show that the developed fault detection algorithm is an effective method to detect faults.

Fig.13
figure 13

a Experimental setup of cascaded half-bridge MLI with PC b output voltage with no-fault

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7 Comparative analysis of proposed converter

The proposed MLI is compared with the MLI present in the literature in terms of number of switches, number of redundancies require for FDI scheme, requirement of redundant switches with increase in the number levels, cost of the converter. The comparative analysis is shown in Table 7. For the comparison purpose the cost of converter is calculated solely based on the switch. This comparison considers the cost of each switch controlled switch along with driver circuit is considered ‘x’. The comparison does not consider the cost of diodes as their cost is significantly lower compared to the controlled switch.

Table 7 Comparative analysis of MLI with proposed MLI
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8 Conclusion

The proposed Modified Cascaded Half-Bridge MLI with PC with \(\frac{m + 9}{2}\) has the least number of switches when compared with topologies present in literature. This circuit has an inherent fault isolation property. Due to its low number of switches, it requires less complicated control and fewer driver circuits. This reduces the overall cost of MLI when compared to other RPC-MLI. The proposed MLI has a high potential for adoption in PV power plants as an integral part of transformerless and filterless system with the above advantages. A Petrub and Observe algorithm is utilized to track the maximum power point. The response time of the algorithm is 2 seconds. A nine-level and seven level version of proposed converter has been simulated in MATLAB. The THD for a proposed for nine level MLI is 7.94% with PV input and 5.86% with constant DC input due to adoption of SHE method solved by the GSA algorithm. The obtained THD is within the limits set by IEEE STD-519-2014 for system under 1 kV of line.

This paper concentrates on the development of an MLI with a reduced number of switches and a high possibility of fault isolation. A simple FDI algorithm for all the controlled switches has been proposed based on the obtained energy levels of the third level approximate and detailed coefficient obtained by the application of MRA to the output voltage. Table 7 provides a comparison of proposed converter and other RPC-MLI in terms of number of switches and fault isolation capability.

During open circuit faults, the voltage level and power supplied by the system reduce; thus, proper energy management systems and voltage controlling devices such as SVC and STATCOM are required, which also acts as reactive power sources for the inverter. If a fault occurs in one half-bridge of a particular phase in three-phase systems, then corresponding switches in another phase will be removed to provide a balanced supply. The energy levels of switch ‘F’are dependent on load, as load does not remain constant in a PV power plant system, another technique needs to be developed for the fault detection of Switch ‘F.’ The work has to be further enhanced for a practical implementation by considering following issues.

  • A grid integration algorithm has to be studied such that a proper power flow can be controlled.

  • The MPPT algorithm can be integrated in the power control algorithm and further studies on the PWM technique has to be designed so that the DC-DC converter can be eliminated.

  • Further improvement has to be done such that the stop in voltage level due to fault condition does not affect the performance.