A 3-stage RF down-converter network for portable, wearable 5G applications

Abstract

The emerging 5G internet-of-things applications in home automation, smart wearables, healthcare monitoring, automotive sensors require low-cost, area efficient, high-performance and low power radio frequency blocks for effective short-range communication. This growing market demand is addressed in this paper by proposing a fully CMOS RF down-converter (RFDC) network for 5G applications. This work aims to achieve high linearity, low noise figure and high gain simultaneously by optimally splitting the performance between the three stages of the RFDC. The proposed down-conversion system is designed in UMC 180 nm CMOS process technology and the post-layout simulations on layout extracted parameters with Cadence SpectreRF shows an IIP3 of − 3.43 dBm, an IIP2 of 78.13 dBm, double-sideband noise figure of 12.76 dB, a conversion gain of 23.69 dB, the spurious-free dynamic range of 71.7 dB, and the phase noise of − 91.39 dBc/Hz at an offset of 5 MHz. The proposed frequency translation circuit occupies a core area of only 0.0043 mm² and consumes a low power of 12.6 mW from a 1.8 V supply.

1 Introduction

The evolution of telecommunication technologies is unprecedented in recent history with the advent of Internet-of-Things (IoT). The IoT applications are based on the standards framed by IEEE for low-rate wireless personal area networks (LR-WPAN) [1, 2] to operate in the 868/915 MHz band and the 2.4 GHz band. The specifications of IEEE for LR-WPAN explicitly necessitate a low-cost communication system to operate in the frequency band of interest. Hence, the direct-conversion receiver architecture is again gaining prominence over the heterodyne architecture because of the simple, low-cost, direct down-conversion mechanism. Also, the growing technology trends of miniaturization can be aided by the direct-conversion architectures. The wireless sensor networks (WSN) in the short-range communication environment can be micro-managed by a more extensive network or networks such as the Metropolitan Area Network (MAN) and Wide Area Network (WAN). The interaction between the 5G networks should have good quality-of-service (QoS) for reliable wireless communication. However, the QoS of the short-range communication environment in the 2.4 GHz ISM band is hindered by the adverse nonlinearities in the continually brimming network.

Although the direct-conversion systems have benefits in complex silicon integration, these systems have limiting factors due to the second-order and the third-order nonlinearities [3,4,5]. The use of the 2.4 GHz ISM band by multiple users/applications create additional unwanted tones at the input of any 2.4 GHz wireless receiver. For the direct-conversion receivers employing CMOS devices in this day and age, the inevitable nonlinear V–I conversion of the multi-tone input signal by the Metal–Oxide–Semiconductor (MOS) devices create harmonic distortion (HD) and intermodulation distortion (IMD). These nonlinearities are characterized by the second-order intercept point (IP2) and the third-order intercept point (IP3). The direct-conversion wireless systems must have a very high input-referred second-order intercept point (IIP2) [6, 7]. In an ideal, balanced differential system, IIP2 is infinite. However, due to device mismatches and other second-order mechanisms [8,9,10], the IIP2 is no longer infinite but tends to a finite value. The input-referred third-order intercept point (IIP3) determines the dynamic range of the entire wireless receiver, and hence, a higher value of IIP3 is advantageous for distortionless operation and thereby to provide suitable QoS.

The need for high linearity in the direct-conversion system places a trade-off on the conversion gain and the noise figure. The linearity of the last stage in the RF chain largely determines the linearity of the entire system [9]. The RF down-converter is required to facilitate the dynamic range improvement of the wireless system, while substantial contribution to the overall gain and noise figure by the mixer stage is an added benefit to the entire wireless system. Along with the direct-conversion architecture, further cost reduction can be achieved by reducing the area hungry passive devices. Thus, novel circuit techniques employing only MOS devices can further boost the realization of the low-cost requirements of the IEEE 802.15.4 standard. However, the MOS devices limit the noise performance of the circuit due to their inherent flicker noise. Therefore, for satisfying the low-cost specifications of the LR-WPAN standard, the emerging short-range communication systems must be implemented with circuits providing proper gain, noise figure and linearity performance while exploiting minimum silicon chip area.

To achieve the linearity requirements of the LR-WPAN direct-conversion systems using CS input stages, the first-order transconductance ($g_{m}^{1}$) must be increased, or the third-order transconductance ($g_{m}^{3}$) must be reduced or nullified. Some of the common-source based RF down-converters are reported in [11,12,13,14,15,16,17]. In [11], 3.1–10.6 GHz RFDC is reported with 22.5 dB gain and − 11 dBm IIP3. In [12], slightly lesser gain but improved linearity performance is reported with a power consumption of 24.5 mW. In [13], 5.8–13 GHz RF front-end for software-defined radio (SDR) is proposed with 25.6 dB gain, 2.6–5.1 dBm IIP3 by making use of the area hungry passive inductors. A digitally controlled RF front-end is recently reported in [15] with 24 dB gain and − 44 dBm IIP3. Alternatively, the direct-conversion systems can be implemented with a trans-impedance amplifier (TIA) input stage to reduce the effect of nonlinear V-I conversion. Some of the common gate (CG) based down-conversion circuits are reported in [18, 19]. In [18], a CG based input transconductance stage is used in the RFDC yielding 15.5 dB gain, 6.2 dB NF and 1-dB compression point at − 12 dBm. In [19], linearity is compromised to yield a high gain of 38.4 dB and a noise figure of 16.7 dB. The high conversion gains reported in [11, 13, 15, 19] will prove fruitful for reducing the overall noise figure of the wireless system and also helps to reduce the number of gain stages required in the receiver chain. High IIP3 provides a higher dynamic range for distortionless operation of the wireless system. The trade-off sacrifices at least one of the performance parameters to gain the other in [11,12,13,14,15,16,17,18,19] while consuming large die area. However, modern deep sub-micron silicon process further complicates the gain and linearity trade-off in RF circuits. Hence, a new circuit design methodology is required to have a high conversion gain, low NF and high IIP3 simultaneously when operating in dense environments such as the 2.4 GHz ISM band.

The current technology trend of miniaturized communication devices places stringent goals of providing high-performance in the lowest silicon area possible. The circuits reported in the literature establish the challenge of providing the highest performance in the smallest chip area possible. This paper aims to give a solution to the challenge of designing and implementing high linear, low noise and high gain RF down-converter network for IEEE 802.15.4 LR-WPAN application. Also, the reported works concentrate on techniques to improve any one of the parameters while this proposed work aims to achieve high gain, low noise figure and high gain simultaneously by optimally splitting the circuit performance between the different stages of the RF down-converter. The proposed methodology is shown in Fig. 1. The switching stage is controlled by a novel 2-stage ring voltage-controlled oscillator (VCO) with a control input to switch ON/OFF the oscillations when required.

Fig. 1

a Conventional mixing stage b proposed RFDC stage

To aid in the frequency conversion, the LO signal is needed along with the frequency translation circuit. Some of the mixer and VCO co-designs are reported in [20,21,22]. The VCOs are realized using LC tank circuits. The phase noise reported for an offset of 1 MHz are 116.2 dBc/Hz in [20], 116.7 dBc/Hz in [21] and 116.8 dBc/Hz in [22]. The LC tank circuit consumes large silicon area, and hence, the low-cost solution for the IEEE 802.15.4 standard is unachievable. For low-cost minimum silicon area consumption, ring based VCO topology is preferred. However, the ring VCO topology suffers from poor spectral purity when compared to LC-tank based oscillators and thus, presents a new challenge of designing ring based VCO with phase noise performance meeting the specifications of IEEE 802.15.4 standard. The reported mixer and VCO networks [20,21,22] also suffer from poor gain and linearity characteristics along with large silicon area consumption. The specifications for the wireless system performance as per IEEE 802.15.4 is listed in Table 1 based on data from [1] and [2].

Table 1 IEEE 802.15.4 down-converter requirements

The equations for gain, noise figure and linearity are derived and examined for trade-offs to suitably design the RF down-converter. The design, parasitic modelling, layout, and post-layout simulation of the RFDC and VCO network for the 2.4 GHz system is carried out in UMC 180 nm CMOS technology using Cadence SpectreRF tool. The process, voltage, temperature (PVT) variation analysis, corner analysis and mismatch analysis for various performance parameters is carried out to establish the reliability of the proposed network for reliable wireless industrial communications. The design of the RFDC network is presented in the Sect. 2. Design optimization and trade-offs between conversion gain, noise figure and linearity are discussed in the Sect. 3 with equations for linearity and NF. The performance analysis of the mixer and VCO is characterized in the Sect. 4 and the Sect. 5 concludes the proposed work.

2 Proposed frequency conversion circuit

2.1 Mixer

The schematic diagram of the conventional mixer and the proposed 3-stage RFDC are shown in Fig. 1a, b respectively. The input stage of the conventional mixer senses the input voltage, and the proposed 3-stage frequency conversion circuit senses the input current instead of the input voltage. In conventional mixing stage, the input matching is not easily achieved whereas, in proposed RFDC, the input resistance can be set to $1/{\text{g}}_{\text{m}}$ of the input transistor. Also, in conventional mixers, the load is passive while in the proposed RFDC, the load is replaced by another gain stage. Thus enabling the proposed RFDC to provide better gain and reduced NF. The proposed 3-stage frequency converter circuit is shown in Fig. 2. The corresponding equivalent circuit is given in Fig. 3. The input RF signal is sensed at the source of the NMOS CG devices $T_{1}$ and T₂. $V_{b}$ is the gate voltage for the common-gate transistors. The transistors $MT_{1}$ and $MT_{2}$ provide the necessary bias at the source of transistors $T_{1}$ and $T_{2}$. $V_{cs}$ provides the necessary bias voltage for the transistors $MT_{1}$ and $MT_{2}$. The RF input is processed by the TIA stage, and the output from the drain of the TIA transistors is fed to the mixing stage (switching stage). The use of PMOS transistors in the switching stage helps in keeping the flicker noise contribution of the MOS devices to a minimum. The equation for flicker noise is modelled in [23] and [24] as

$$ \widehat{{V_{n}^{2} }} = \frac{{K_{f} I_{D}^{\alpha f} }}{{C_{ox} \cdot W \cdot L}} \cdot \frac{1}{f} $$

(1)

where $K_{f}$ and $\alpha f$ are process dependent, C_ox is the gate-oxide capacitance, f is the frequency, WxL is the area of the MOS device. Since PMOS devices have lower mobility than the NMOS devices, the flicker noise contribution is minimized. Depending upon the polarity of the local oscillator (LO) signal $V_{lo}$, one of the switching transistors provide the signal path from the TIA stage to the gain boosting stage. The mixing stage is a double-balanced stage, and the output of the mixing stage is the input to the final stage for gain boosting. Although the LO signal is a large signal for effective switching function, the transistors $T_{3 - 6}$ provide a time-varying resistive path from current sensing stage to the gain boosting stage. This resistive path is modelled as $r_{03,4,5,6}$ for numerical analysis. The PMOS transistors $T_{7}$ and T₈ sense the signal from the switching stage and the intermediate frequency (IF) output signal (V_if) is available at the drain of the PMOS transistors. The necessary potential for the drain of PMOS transistors is provided by the NMOS load transistors MT₃ and MT₄. V_tail is the gate bias for the transistors MT₃ and MT₄. The proposed 3-stage frequency converter circuit is analysed for conversion gain calculations as follows. The gain equations are derived as a function of the equivalent RF voltage (V_rf) sensed at the source node of the input current sensing transistors. The analysis follows the methodology reported in [11, 16, 25]. The RF signal voltage (V_rf) with amplitude (A_rf) and frequency (ω_rf) in radians can be expressed as

$$ V_{rf} = A_{rf} \cos (\omega_{rf} t) $$

(2)

moreover, the local oscillator signal (V_lo) with amplitude (A_lo) and frequency in radians (ω_lo) generated by the VCO expressed as

$$ V_{lo} = A_{lo} \cos (\omega_{lo} t) $$

(3)

then the down-converted IF signal (V_if) is derived based on [25, 26] as

$$ V_{if} \approx \frac{1}{\pi } \cdot G_{0} \cdot A_{rf} \cdot \cos (\omega_{rf} - \omega_{lo} )t $$

(4)

Fig. 2

Proposed CG based RF mixer circuit

Fig. 3

Equivalent circuit model for the proposed 3-stage RF mixer

The IF signal in (4) can be simplified as

$$ V_{if} \approx \frac{1}{\pi } \cdot G_{0} \cdot A_{rf} \cdot \cos \left( {\omega_{if} t} \right) $$

(5)

where $G_{O}$ is the gain factor, and ω_if is the frequency of the IF signal in radians and is expressed as

$$ \omega_{if} = \omega_{rf} - \omega_{lo} $$

(6)

The (${\raise0.7ex\hbox{$1$} \!\mathord{\left/ {\vphantom {1 \pi }}\right.\kern-0pt} \!\lower0.7ex\hbox{$\pi $}}$) term comes from the first harmonic of the Fourier expansion of the LO signal applied to the mixer. Thus, from (5), the conversion gain (G_c) for a double-balanced mixer is expressed as

$$ G_{c} \approx \frac{4}{\pi } \cdot G_{0} $$

(7)

The gain factor (G_O) can be calculated from the equivalent circuit in Fig. 3 as follows. Since, the first stage seen by the input RF signal is a TIA stage, the gain from the input (V_rf) to the node V_x can be derived as

$$ \frac{{V_{x} }}{{V_{rf} }} \approx g_{m1,2} .(r_{o1,2} ||r_{oI1,I2} ) $$

(8)

where, g_m1,2 is the transconductance of the input transistor T_1.2, r_o1,2 is the output resistance of the input transistor T_1.2 and r_oI1,I2 is the output resistance of the PMOS current source I_1.2.

The switching transistors (T_3-6) provide the signal path from node V_x to node V_y depending on the polarity of the LO signal. At any given point in time, only one transistor is switched ON by the LO signal, and the ON transistor acts as a resistive path between the two nodes, V_x and V_y. The gain from node V_x to node V_y is almost equal to 1 and can be easily derived from the voltage divider shown in Fig. 4.

Fig. 4

Voltage divider model for the signal path from $V_{x}$ to $V_{y}$

The ON resistance of the switching transistors T_3-6 is modelled as r_03,4,5,6. At the node V_y, the signal encounters the poly-silicon gate of the gain boosting transistors T_7,8. Hence, the signal path is modelled with a large resistance of r_large to include the very high resistance of the polysilicon layer and the gate oxide (SiO₂) layer. By applying voltage division at V_y, we have

$$ \frac{{V_{y} }}{{V_{x} }} = \frac{{r_{large} }}{{r_{o3,4,5,6} + r_{large} }} \cdot f\left[ {v_{lo} } \right] $$

(9)

$$ \frac{{V_{y} }}{{V_{x} }} \approx 1 \cdot f\left[ {v_{lo} } \right] $$

(10)

From (10), it can be seen that almost all of the signal at node V_x is available at the input node of the gain boosting transistors, V_y after frequency conversion by the switching transistors. The frequency conversion is represented as a function of the LO signal, $f\left[ {v_{lo} } \right]$. The PMOS transistors T₇ and T₈ offer differential common-source amplification to the frequency-converted IF signal, and the amplified output IF signal is available at the drain of the PMOS transistors. The output resistance of the switching transistor is a nonlinear function of the LO signal [24, 25]. Thus, the RF signal is modulated by the LO signal and hence, the gain offered by the circuit is dependent on the LO signal. The gain of the signal from V_y to V_if can be derived from the equivalent circuit in Fig. 3 as

$$ \left| {\frac{{V_{if} }}{{V_{y} }}} \right| \approx g_{m7,8} \cdot (r_{o7,8} | |r_{oMT3,4} )\cdot f\left[ {v_{lo} } \right] $$

(11)

where,g_m7,8 is the transconductance of the PMOS transistor T_7,8, r_o7,8 is the output resistance of the PMOS transistor T_7,8 and $r_{oMT3,4}$ is the output resistance of the NMOS load transistors MT_3,4.

From (8), (10), and (11), the overall gain from the input (V_rf) to the output (V_if) can be expressed as

$$ G_{0} = \frac{{V_{x} }}{{V_{rf} }}.\frac{{V_{y} }}{{V_{x} }}.\frac{{V_{if} }}{{V_{y} }} $$

(12)

$$ G_{0} \approx g_{m1,2} \cdot (r_{o1,2} | |r_{oI1,2} )\cdot g_{m7,8} \cdot (r_{o7,8} | |r_{oMT3,4} )\cdot f\left[ {v_{lo} } \right] $$

(13)

Thus, by substituting the value of G_O from (13) in (7), the conversion gain for the proposed mixer circuit can be expressed as

$$ G_{c} \approx \frac{4}{\pi } \cdot g_{m1.2} \cdot (r_{o1,2} | |r_{oI1,2} )\cdot g_{m7,8} \cdot (r_{o7,8} | |r_{oMT3,4} )\cdot f\left[ {v_{lo} } \right] $$

(14)

The above Eq. (14) provides insights into the optimization of the circuit about conversion gain, noise figure, and linearity. In (14), the transconductance of the input transistors in the TIA stage (g_m1,2) is optimized for the impedance matching, linearity and noise figure and the transconductance of the gain boosting CS stage transistors (g_m7,8) is optimized for gain. The linearity analysis, optimizations and, trade-offs are discussed in the Sect. 3.

2.2 Voltage controlled oscillator (VCO)

Ring VCO is preferred over LC tank based VCO because the latter’s silicon consumption in the chip affects the low-cost metric necessary for the IEEE 802.15.4 LR-WPAN standards. In the proposed work, the ring oscillator (RO) is designed with only two delay stages and a NAND gate for controlling the oscillation based on ($\overline{EN}$) signal for low power operation. Some of the ROs implemented with an even number of stages are reported in [27, 28]. The proposed 2-stage ring VCO with enable input ($\overline{EN}$) is shown in Fig. 5. The $\overline{EN}$ signal helps to shut down the VCO circuit when necessary to minimize the power consumption. This arrangement helps in saving battery life of the devices in LR-WPAN wireless applications. Each stage of the VCO is a current starved inverter made up of PMOS transistors M_1,3 and NMOS transistors M_2.4. The transistors B₁ and B₂ act as tail current sources to stage-I and stage-II respectively. When $\overline{EN}$ goes logic high, the signal in the feedback path (f/b) is inverted and produced at the output of the NAND gate. The inverter stages provide further polarity reversal, and the cycle continues. When $\overline{EN}$ goes logic low, and if the signal in the feedback path is logic high, then no polarity reversal takes place in the feedback path. Hence, the oscillation ceases. Thus, by using enable input, the power consumption of the VCO can be reduced. Table 2 shows the truth table for the VCO with enable input. S₁ and S₂ are the input nodes to stage I and stage II respectively. The transient response of the 2-stage ring oscillator is shown in Fig. 6. The LO signal swings between VDD and Gnd resulting in a peak-to-peak swing of 1.8V_pp. The VCO is designed to operate at near rail-to-rail swing from a 1.8-V power supply. The rail to rail swing favours hard switching of the mixer stage and also in reducing the noise contribution of the switching transistors.

Fig. 5

Proposed 2-stage ring VCO

Table 2 Truth table for proposed VCO with enable input

Fig. 6

Transient response of the 2-stage ring oscillator

The frequency of oscillation is calculated in [29, 30] and can be simplified as

$$ f \approx \frac{{I_{bias} }}{{2N.V_{sw} .C_{in} }} $$

(15)

where, I_bias is the bias current through the delay stage of the VCO, V_sw is the voltage at the load, C_in is the capacitance at the gate of the delay stage, and N is the number of delay stages.

For rail-to-rail swing, the delay stages are biased at (${\raise0.7ex\hbox{${Vdd}$} \!\mathord{\left/ {\vphantom {{Vdd} 2}}\right.\kern-0pt} \!\lower0.7ex\hbox{$2$}})$. Hence, the gate capacitance can be simplified as

$$ C_{in} \approx \frac{2}{3}.WLC_{ox} $$

(16)

where, WL is the area of the MOS device, and The gate-oxide capacitance is given as

$$ C_{ox} = \frac{{\varepsilon_{ox} }}{{t_{ox} }} $$

(17)

where ɛ_ox is the permittivity and t_ox is the thickness of the SiO₂ layer respectively.

Since the load to any inverter delay stage in Fig. 5 is another delay stage, V_sw is equal to V_gs. Also, rewriting the bias current of the delay stage (I_bias) as the product of transconductance (g_m) and the gate to source voltage (V_gs), (15) can be represented as

$$ f \approx \frac{{g_{m} }}{{2N \cdot C_{in} }} $$

(18)

The transconductance (g_m) in (18) can be rewritten as a function of the bias current (I_bias) as

$$ f \approx \frac{{2I_{bias} }}{{2N.\left( {V_{gs} - \left| {V_{T} } \right|} \right) \cdot C_{in} }} $$

(19)

The frequency of oscillation is verified by performing a 512-point Fourier Transform (FT) on the transient signal, and the magnitude spectrum of the LO signal is plotted in Fig. 7. Thus, from (19), by controlling the I_bias, the frequency of oscillation can be varied. The two bias voltages V_b1 and V_b2, for the tail transistors B₁ and B₂, aids in controlling the bias current and thereby, the frequency of oscillation (f).

Fig. 7

DFT of the LO signal at 2.4 GHz

The phase noise (PN) power contribution of the ring VCO is the sum of PN power contributed by the delay stages $i\widehat{{_{n,delay}^{2} }}$ and the phase noise power of the NAND gate $i\widehat{{_{n,NAND}^{2} }}$. The total PN power can be given as

$$ i\widehat{{_{PN,VCO}^{2} }} = i\widehat{{_{n,delay}^{2} }} + i\widehat{{_{n,NAND}^{2} }} $$

(20)

where,

$$ i\widehat{{_{n,delay}^{2} }} = i\widehat{{_{M1}^{2} }} + i\widehat{{_{M3}^{2} }} + i\widehat{{_{B1}^{2} }} + i\widehat{{_{B2}^{2} }} $$

(21)

$$ i\widehat{{_{n,NAND}^{2} }} = i\widehat{{_{A1}^{2} }} + i\widehat{{_{A3}^{2} }} + i\widehat{{_{A4}^{2} }} $$

(22)

In (21) and (22), the noise power of transistors $M_{1}$, $M_{3}$, $B_{1}$ and B₂ are represented as $i\widehat{{_{M1}^{2} }}$, $i\widehat{{_{M3}^{2} }}$, $i\widehat{{_{B1}^{2} }}$ and $i\widehat{{_{B2}^{2} }}$ respectively. Similarly, the noise power of transistors in the NAND gate $A_{1}$, $A_{3}$, and $A_{4}$ are represented as $i\widehat{{_{A1}^{2} }}$, $i\widehat{{_{A3}^{2} }}$ and $i\widehat{{_{A4}^{2} }}$ respectively. It should be noted that the noise contribution of transistors $M_{2}$, $M_{4}$ and $A_{2}$ are neglected since these transistors are cascode transistors in the 2-stage ring VCO of Fig. 5 and they do not contribute to the output noise.

3 Design and optimization trade-offs between conversion gain, noise figure, and linearity

From (14), we can see that the conversion gain of the mixer circuit depends on the transconductance of the input transistors ($g_{m1,2}$) and the transconductance of the gain boosting devices ($g_{m7,8}$). The input stage senses the input signal current directly and hence the effect of nonlinearity is subdued. The gain boosting stage differential pair ($T_{7,8}$) is the primary source of nonlinearity in the proposed mixer since the gain boosting stage senses voltage at the gate and produces an equivalent current at the drain by virtue of the nonlinear transconductance effect. When the PMOS and NMOS devices operate in the saturation region, the inherent nonlinearity is evident from the $I_{D}$ versus $V_{Ds}$ characteristics. By expanding the output drain current ($i_{out}$) of the MOS devices as a function of the input gate to source voltage ($v_{in}$) in Taylor series, we get,

$$ i_{out} \approx g_{m}^{1} v_{in} + g_{m}^{2} v_{in}^{2} + \cdots + g_{m}^{n} v_{in}^{n} $$

(23)

where,

$$ g_{m}^{n} = \frac{1}{n!} \cdot \frac{{\partial^{n} }}{{\partial v_{in}^{n} }}\left( {i_{out} } \right) $$

(24)

Equation (24) gives the nth-order derivative of the output drain current as a function of the input gate to source voltage. In RF systems, the first three terms of (23) are the elementary sources of nonlinearity, and hence, the analysis is restricted to the first three terms. For an input signal ($v_{in}$) expressed as

$$ v_{in} = A_{in} \cdot \cos \left( {\omega_{in} t} \right) $$

(25)

The nonlinear relation in (23) yields frequency components at ω_in, 2ω_in, 3ω_in. The frequency components at 2ω_in and 3ω_in are filtered out as they occur outside the required frequency band in RF applications. However, since the 2.4 GHz band is shared by multiple users/applications such as Wi-Fi, WiMax, Bluetooth, MobileFi, LTE, more than a single tone may be present at the input of the down-conversion system. This multi-tone input signal having frequency components, for example, ω₁ and ω₂, are closely spaced with each other and can be expressed as

$$ v_{in} = A_{1} \cos \left( {\omega_{1} t} \right) + A_{2} \cos \left( {\omega_{2} t} \right) $$

(26)

Equation (26) produces the in-band frequency components when substituted and expanded in (23). The expansion of (23) for multi-tone input in (26) is analysed in [26], and the derivation shows second-order intermodulation (IM) products at $\omega_{1} \pm \omega_{2}$, and the third-order intermodulation products at $2\omega_{1} \pm \omega_{2}$ and $2\omega_{2} \pm \omega_{1}$. These in-band frequency components are hard to be filtered, and hence, they are the primary sources of nonlinearity in the RF systems. The IM products $\omega_{1} - \omega_{2}$, $2\omega_{1} - \omega_{2}$ and $2\omega_{2} - \omega_{1}$ are of particular interest as they are spaced close to the fundamental components ω₁ and ω₂. Any nth order IM product grows n-times faster than the fundamental and causes the system to compress the desired signal, resulting in distortion. The IP2 and IP3 can be defined as

$$ IP2 = \frac{{g_{m}^{1} }}{{g_{m}^{2} }} $$

(27)

$$ IP3 = \sqrt {\frac{4}{3}.\frac{{g_{m}^{1} }}{{g_{m}^{3} }}} $$

(28)

where, $g_{m}^{n}$ is the nth order transconductance of the operating device. From (27) and (28), increasing the first-order transconductance $g_{m}^{1}$ will increase both the intercept points. The increase in $g_{m}^{1}$ is not straightforward since this increases the bias current. Alternatively, $g_{m}^{2}$ and $g_{m}^{3}$ can be reduced or nullified to increase IP2 and IP3 respectively. Another alternative is to bypass the transconductance effect by sensing the currents directly at the input and processing it further, and this approach is followed in this proposed work. The proposed mixer is a cascade of current sensing, switching and gain boosting stages. Hence, the overall IP3 must include the transconductance of the current sensing stage, transconductance of the gain boosting stage and the gain of the current sensing stage. Therefore, following the analysis based on [23,24,25,26], the IP2 and the IP3 points are derived following extensive calculations as the following:

$$ IP2 = \frac{{\frac{{G_{m,CG}^{1} }}{{G_{m,CG}^{2} }} \cdot \frac{{g_{m,CS} }}{{g_{m,CS}^{\prime } }} \cdot \left( {1 + S_{0} } \right)^{2} }}{{\frac{{g_{m,CS} }}{{g_{m,CS}^{\prime } }}\left( {1 + S_{0} } \right)^{2} + \frac{{G_{m,CG}^{1} }}{{G_{m,CG}^{2} }} \cdot A_{v,CG}^{2} \cdot f\left( {LO} \right)}} $$

(29)

$$ IP3 = \frac{{4/3\sqrt {\frac{{\left( {1 + S_{0} } \right)^{3} }}{{\left( {1 - \frac{{2(g_{m,CS}^{\prime } )^{2} }}{{g_{m,CS} .g_{m,CS}^{\prime \prime } }} \cdot \frac{{S_{0} }}{{1 + S_{0} }}} \right)}}\frac{{G_{m,CG}^{1} }}{{G_{m,CG}^{3} }} \cdot \frac{{g_{m,CS} }}{{g_{m,CS}^{''} }}} }}{{\sqrt {\frac{4}{3}} \cdot \sqrt {\frac{{\left( {1 + S_{0} } \right)^{3} }}{{\left( {1 - \frac{{2(g_{m,CS}^{\prime } )^{2} }}{{g_{m,CS} .g_{m,CS}^{\prime \prime } }} \cdot \frac{{S_{0} }}{{1 + S_{0} }}} \right)}} \cdot \frac{{g_{m,CS} }}{{g_{m,CS}^{\prime \prime } }}} + \sqrt {\frac{4}{3} \cdot \frac{{G_{m,CG}^{1} }}{{G_{m,CG}^{3} }}} \cdot A_{v,CG}^{2} \cdot f\left( {LO} \right)}} $$

(30)

In (29) and (30), $S_{0}$ is the feedback factor in the gain boosting stage, $g_{m,CS}$ is the first-order transconductance of the gain boosting CS stage, $g_{m,CS}^{\prime }$ and $g_{m,CS}^{\prime \prime }$ are the second- and third-order derivative of the transconductance of the CS stage respectively. $G_{m,CG}^{n}$ is the nth-order effective transconductance of the current sensing stage, $A_{v,CG}$ is the gain of the current sensing stage. The equations are derived based on the schematic of Fig. 2. From (14), (29) and (30), the design trade-offs between linearity and gain can be analysed. The linearity is inversely proportional to the gain of the current sensing stage and the LO signal. However, the overall nonlinear transconductance effect on the signal is minimized, resulting in high IP2 and IP3 values elaborated in the Sect. 4. To find the trade-off between linearity and noise figure, the overall NF has to be derived. The overall NF is contributed by the input current sensing stage, the switching stage, and the gain boosting stage. The noise factor of the input stage is simplified in [31] and is given as

$$ F_{CG} = 1 + \frac{\gamma }{\alpha } \cdot \frac{1}{{g_{m} R_{s} }} $$

(31)

In (31), γ and α, are technology-dependent, and since the transconductance ($g_{m} )$ of the input stage transistor is designed to be equal to ($1/R_{s}$) for input matching, the noise factor of the input stage from (31) is found to be constant for a particular process. Fixing the $g_{m}$ of the input CG stage for providing proper input matching creates a bottle-neck for improving gain. Hence, the gain of the overall down-converter circuit is concentrated in the CS gain boosting stage. The feedback path offered by the gate to drain capacitance ($C_{gd}$) to IM products is grounded since the gate is an AC ground in the current sensing stage. This also makes the input stage more linear than the gain boosting stage. Thus, the input current sensing stage concentrates on linearity and matching while gain boosting stage provides the necessary amplification for the RF signal. The gain boosting stage biasing is appropriately chosen to keep the third-order transconductance $g_{m}^{3}$ to a minimum. Thus, the gain boosting stage of the 3-stage mixer is optimized for both gain and linearity enhancement of the down-conversion system.

Noise contribution of the down-converter circuit is mainly due to the mixing action of the switching transistors. The noise contribution to the output of a double-balanced mixer is generalized in [26] as

$$ v\widehat{{_{o,switch}^{2} }} = 8kTR_{L} \left( {1 + \gamma \frac{{2R_{L} I}}{{\pi A_{lo} }} + \gamma g_{m} R_{L} } \right) $$

(32)

In (32), $k$ is the Boltzmann constant, $T$ is the temperature in Kelvin, $R_{L}$ is the load resistance, $\gamma$ is a process dependent factor, $A_{lo}$ is the amplitude of the LO signal, and I is the bias current. Since the A_lo is inversely proportional to the output noise, increasing the LO signal amplitude is advantageous for reducing the noise contribution of the mixer. Finally, the noise contribution of the CS stage is calculated as follows.

$$ v\widehat{{_{o,CS}^{2} }} = \left( {i\widehat{{_{T7}^{2} }} + i\widehat{{_{T8}^{2} }} + i\widehat{{_{MT3}^{2} }} + i\widehat{{_{MT4}^{2} }}} \right)(r_{07,8} ||r_{oMT3,4} )^{2} $$

(33)

In (33), the noise contribution of transistors $T_{7}$, $T_{8}$, $MT_{3}$ and $MT_{4}$ are represented by their noise power as $i\widehat{{_{T7}^{2} }}$, $i\widehat{{_{T8}^{2} }},\; i\widehat{{_{MT3}^{2} }}$ and $i\widehat{{_{MT4}^{2} }}$ respectively. If $i\widehat{{_{T7}^{2} }}$ = $i\widehat{{_{T8}^{2} }}$ = $i\widehat{{_{T}^{2} }}$ and $i\widehat{{_{MT3}^{2} }}$ = $i\widehat{{_{MT4}^{2} }}$ = $i\widehat{{_{MT}^{2} }}$, then (33) can be reduced as

$$ v\widehat{{_{o,CS}^{2} }} = 2\left( {i\widehat{{_{T}^{2} }} + i\widehat{{_{MT}^{2} }}} \right) \cdot (r_{07,8} ||r_{oMT3,4} )^{2} $$

(34)

where,

$$ i\widehat{{_{T}^{2} }} = \frac{8kT}{3} \cdot g_{mT7,8} + \frac{{K_{f} \cdot I_{D}^{\alpha f} }}{{f \cdot \left( {c_{ox}^{2} \cdot W \cdot L} \right)_{T7,8} }} $$

(35)

$$ i\widehat{{_{MT}^{2} }} = \frac{8kT}{3} \cdot g_{mMT3,4} + \frac{{K_{f} \cdot I_{D}^{\alpha f} }}{{f \cdot \left( {c_{ox}^{2} \cdot W \cdot L} \right)_{MT3,4} }} $$

(36)

Thus, from (31), (32) and (34), the overall noise contribution of the RF down-converter can be expressed as

$$ NF \approx 1 + \frac{\gamma }{\alpha } \cdot \frac{1}{{g_{m} R_{s} }} + \frac{{v\widehat{{_{o,switch}^{2} }}}}{{A_{v, CG} \cdot \left( {1^{2} } \right)}} + \frac{{v\widehat{{_{o, CS}^{2} }}}}{{A_{v, CG} \cdot A_{v,CS}^{2} }} $$

(37)

The above Eq. (37) shows the NF dependence on the LO signal, the gain of the current sensing stage and gain boosting stage. Also, from (29) and (30), the LO signal is inversely proportional to linearity. Hence, in the proposed mixer and VCO network, the VCO is designed to operate from rail-to-rail as mentioned earlier in the Sect. 2. By Friis’ equation [26], the noise factor of the mixer stage is reduced by the gain of the preceding Low-Noise Amplifier (LNA) and thus, relaxing the noise performance requirement of the mixer. In this work, the noise contribution due to the flicker noise of the MOS transistors is minimized by employing PMOS switching devices for mixing action instead of NMOS devices. Since the output of the mixing stage encounters a very high resistance in the form of polysilicon gate of the gain boosting stage, the current through the mixing transistors ($T_{3 - 6}$) is drastically reduced aiding in the reduction of the flicker noise contribution modelled in (1). Furthermore, the input stage has an optimized noise performance for a specific process. In this work, the NF is optimized by gain of the gain boosting stage transistors $T_{7,8}$ and the LO signal. Linearity is optimized by the gain of the input stage transistor $T_{1,2}$.

Thus, the trade-offs between the gain, linearity and noise figure are divided optimally between the three stages of the mixer. The input stage is optimized for matching and linearity and has a process dependent noise performance. The mixing stage is optimized for noise performance since the mixing stage is the major contributor to noise in the wireless system. Finally, the output stage concentrates on gain improvement and the overall reduction of noise figure along with keeping the growth of third-order tones to a minimum for presenting high dynamic range to the wireless system.

4 Results and discussion

The physical layout of the designed RF down-conversion network is shown in Fig. 8. For calculating the area, the measurement was taken 2λ away from the four sides of the core area. The total silicon area after integrating the RF down-conversion system and including the additional space between the two cores is scaled as 53.75 µm × 80.36 µm. The total layout area of the chip including power rails is 87.35 µm × 114.36 µm. For post-layout validation of the RFDC, BSIM3 models from UMC is used. The wire parasitic from the device terminal to the probe pads is modelled with an inductance, L_wire, of 1nH. The pad capacitance is modelled with a capacitor, C_pad, of 50fF. The model of the test bench with parasitic components is shown in Fig. 9. In reality, the bond-wire inductance and pad capacitance values will be smaller than the values used for modelling in this work. These values are referred from [24]. The bond-wire parasitic modelling helps to compare and calibrate the simulation measurements with the measurements after chip fabrication. This test setup ensures the reliable operation of the circuit after fabrication. The LO signal generated by the VCO swings near rail-to-rail from a 1.8-V power supply. The 1.8 $V_{pp}$ is equivalent to a power level of 9 dBm. The VCO is tuned to 2.4 GHz by the two bias voltages $V_{b1}$ and $V_{b2}$. The required frequency range for IEEE 802.15.4 application is from 2.4 to 2.485 GHz.

Fig. 8

The physical layout of the proposed RF down-converter with probe pads in a core area of 0.00431 mm²

Fig. 9

Modelling of the proposed frequency translation circuit with parasitic components

The bond-wire parasitic is modelled with an inductor of 1nH. Cadence SpectreRF suite is used for RF simulation and measurement of layout extracted parameters (post-layout simulation). Figure 10 shows the variation of conversion gain in the frequency band of interest with and without bond-wire parasitic. It can be seen that without bond-wire parasitic, the conversion gain is 23.79 dB and with bond-wire parasitic, the conversion gain is 23.69 dB with a reduction of only 0.1 dB. The double-sideband noise figure (DSB-NF) is measured against the frequency and is shown in Fig. 11. From Fig. 11, the variation between measurements without bond-wire parasitic and with bond-wire parasitic is found to be very close. From (14) and (37), the dependence of gain and NF on the LO signal power is characterized, and the variation is plotted in Fig. 12.

Fig. 10

Conversion gain (dB) versus input RF frequency (Hz)

Fig. 11

Double-sideband noise figure (dB)

Fig. 12

Variation of gain and NF with LO power

The nonlinearity is characterized by the 1 dB compression point, IP2 and IP3 points in Figs. 13, 14 and 15 respectively using a two-tone test. The designed RF circuit has a 1 dB compression point at − 12.5 dBm. The IIP2 and the IIP3 point with bond-wire parasitic are 78.13 dBm and − 3.43 dBm respectively. The high IIP2 value of 78.13 dBm transcribes into a corresponding IMR2 of 163.13dB as per the relation in [10]. The linearity performance of the frequency translation circuit is a helpful tool to characterize the spurious-free dynamic range (SFDR) of the entire wireless system. If $P_{noise}$ (dBm) is the minimum input noise power level to the circuit, then SFDR can be expressed by definition in [26] as follows:

Fig. 13

1-dB Compression Point

Fig. 14

Second-order intercept point (dBm)

Fig. 15

Third-order intercept point (dBm)

$$ SFDR_{dB} = \frac{2}{3}(IIP3_{dBm} - P_{noise} ) $$

(38)

In (38), $P_{noise}$ is the noise floor of a noiseless receiver with a value of − 111 dBm $\left( { - 174dBm + 10\log BW} \right)$. Thus, by (38) the proposed down-conversion network provides a very high dynamic range of 71.7 dB. The achieved SFDR is higher than the recently proposed down-converters in [15, 16, 18, 19]. The phase noise performance of the 2-stage RO is presented in Fig. 16. The designed RO has a phase noise of − 91.39 dBc/Hz at an offset of 5 MHz. The 5 MHz offset is chosen because the channel spacing is 5 MHz for IEEE 802.15.4 applications. The phase noise performance of the designed oscillator at an offset of 100 MHz is − 125.4 dBc/Hz. For IEEE 802.15.4 systems, the required phase noise performance is − 73.5 dBc/Hz at 5 MHz offset [2]. The designed RO lacks the spectral purity of LC-based oscillators but still provides excellent phase noise performance required in low area of only 137 µm² while consuming a very low power of 100 µW.

Fig. 16

Phase noise (dBc/Hz)

For establishing the reliability and dependability of the proposed RF down-converter, the corner, voltage, and temperature variation analysis are carried out across the required frequency range for conversion gain, noise figure and are shown in Figs. 17, 18, 19, 20, 21, and 22. Table 3 presents the corner, voltage, and temperature variation analysis for IIP2 and IIP3. The process and device mismatch analysis of the proposed down-conversion network is performed using Monte-Carlo simulation for gain, NF, IIP2, IIP3, and phase noise of the VCO at both 5 MHz offset and 100 MHz offset. The Monte-Carlo simulation has been run extensively for 500 samples of the process and device mismatch variation analysis with the maximum deviation (3σ). The histogram of the Monte-Carlo simulation results with the mean (µ) value and the standard deviation (3σ) value is shown in Fig. 23, 24, 25, 26, 27, 28. The Y-axis of the histograms represent the frequency of occurrence of the parameter values, and it is unitless.

Fig. 17

Conversion gain variation with process corners

Fig. 18

Double-sideband noise figure variation with process corners

Fig. 19

Conversion Gain variation with Temperature

Fig. 20

Double-sideband noise figure variation with temperature

Fig. 21

Conversion gain variation with supply voltage

Fig. 22

Double-sideband noise figure variation with supply voltage

Table 3 PVT variation of IIP2 and IIP3

Fig. 23

Histogram of Monte-Carlo simulation for conversion gain

Fig. 24

Histogram of Monte-Carlo simulation for noise figure

Fig. 25

Histogram of Monte-Carlo simulation for IIP2

Fig. 26

Histogram of Monte-Carlo simulation for IIP3

Fig. 27

Histogram of Monte-Carlo simulation for Phase Noise @ 5 MHz offset

Fig. 28

Histogram of Monte-Carlo simulation for Phase Noise @ 100 MHz offset

Feedthrough causes DC offsets and affects the linearity of the wireless system. The feedthrough is caused by the substrate coupling of the strong LO signal in densely integrated systems. The effect of LO feedthrough is characterized by the LO to the RF signal feedthrough and the LO to the IF signal feedthrough. Figures 29 and 30 show the suppressed harmonics of the LO signal in the RF path and the IF path respectively. The fundamental harmonic of the LO signal in the RF path is measured as − 202.3 dB and in the IF path as − 40.17 dB respectively.

Fig. 29

LO to RF feedthrough component

Fig. 30

LO to IF feedthrough component

Finally, the figure-of-merit (FOM) is calculated for comparison of the proposed RF down-conversion network with the existing frequency translation circuits using the following expression

$$ FoM = 10 \cdot \log_{10} \frac{{{10^{G/20} \cdot 10^{{\left( {IIP3 - 10} \right)/20}} }} }{{10^{NF/10} \cdot P.A.10^{PN/10} }} $$

(39)

The Table 4 presents the transistor sizing for the proposed 3-stage down-converter and 2-stage ring network. The Table 5 shows the comparison of the proposed current sensing based 3-stage RFDC against the other current sensing based down-converters and inductorless down-converters reported in the literature. The Table 6 presents the comparison of the proposed mixer and VCO network against some of the existing architectures. It can be seen that the proposed RF down-conversion network performs better than the other reported circuits while consuming the lowest silicon area.

Table 4 Transistor sizing for the proposed RF down-conversion circuit

Table 5 Literature comparison of CG based mixers

Table 6 Literature comparison of mixer and VCO circuit

The proposed RFDC architecture is implemented in 180 nm since the IEEE 802.15.4 protocol specifies low-cost SoC for operation [1, 2]. Also, for sub-6 GHz 5G networks, 180 nm SoC is sufficient for quality performance. However, the proposed RFDC architecture can be implemented in lower technologies based on the bias conditions and aspect ratios required. Thus, the proposed RFDC architecture is unconstrained in its practical application.

5 Conclusion

A novel 3-stage RF down-converter and a 2-stage ring VCO is presented in this work with high linearity, high gain and low noise figure for direct down-conversion receivers employed in 2.4 GHz 5G IoT applications. The proposed network efficiently performs the frequency conversion while consuming only 12.6mW of power from a supply of 1.8 V. The PVT variation analysis and the Monte-Carlo simulations show the reliable, dependable, robust operation of the proposed down-conversion system in the required range of 2.4–2.485 GHz. The IIP2 of 78.13 dBm makes the proposed frequency translation network suitable for direct-conversion receiver architectures and the IIP3 of − 3.43 dBm enhances the overall dynamic range of the wireless receiver for distortionless operation. This makes the communication of data between sensor nodes and data centre to be less error-prone and increases the quality-of-service (QoS) of the network. The high conversion gain of 23.69 dB and noise figure of 12.76 dB helps with the overall noise performance of the wireless receiver, and also the high gain helps in reducing the additional amplification stages required in the receiver chain and thereby, the size of the devices is drastically minimized. The figure-of-merit (FoM) for the proposed network is 229.67, and it is found to be better than the other state-of-the-art down-converter and VCO co-designs reported in the literature. Thus, the proposed RF down-conversion circuit design is well suited for low-cost, low power, reliable, high-performance, area-efficient demands of portable, wearable 5G applications in the 2.4 GHz band without increasing the Bill-of-Materials (BoM) since the performance is available at low power consumption and low silicon area of merely 0.0043 mm².