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Performance Investigation of Bottom Gate ZnO Based TFT for High-Speed Digital Display Circuit Applications

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Abstract

This paper explores possibility of device as well as circuit performance enhancement in the bottom gate \({\text{ZnO}}\) based TFT via Mg and Cd material doping. DC, Analog & RF performance, Energy efficiency and Noise analysis were performed for both doped (i.e., \({{\text{Mg}}}_{{\text{y}}}{{\text{Zn}}}_{1-{\text{y}}}{\text{O}}\) and \({{\text{Cd}}}_{{\text{x}}}{{\text{Zn}}}_{1-{\text{x}}}{\text{O}}\)) and undoped \({\text{ZnO}}\) channel TFT structures. Further, successful circuit implementation of these devices was done in resistive inverter and AMLCD pixel display circuits. Performance wise both \({{\text{Mg}}}_{{\text{y}}}{{\text{Zn}}}_{1-{\text{y}}}{\text{O}}\) and \({{\text{Cd}}}_{{\text{x}}}{{\text{Zn}}}_{1-{\text{x}}}{\text{O}}\) channel TFTs were found to be superior against its undoped variant. ~ 376%, ~ 105% and ~ 162% are the percentage improvement in \({({\text{I}}}_{{\text{ON}}}/{{\text{I}}}_{{\text{OFF}}})\) ratio, field effect mobility \({(\upmu }_{{\text{FE}}})\) and effective mobility \({(\upmu }_{{\text{eff}}})\) for \({{\text{Cd}}}_{{\text{x}}}{{\text{Zn}}}_{1-{\text{x}}}{\text{O}}\) based TFT with respect to \({\text{ZnO}}\) based TFT, same parameters show ~ 194%, ~ 103% and ~ 133% percentage improvement for the case of \({{\text{Mg}}}_{{\text{y}}}{{\text{Zn}}}_{1-{\text{y}}}{\text{O}}\) TFT. Also, ~ 23% is percentage decrease in subthreshold swing (SS) for \({{\text{Cd}}}_{{\text{x}}}{{\text{Zn}}}_{1-{\text{x}}}{\text{O}}\) based TFT with respect to \({\text{ZnO}}\) based, whereas ~ 11% is percentage decrement for \({{\text{Mg}}}_{{\text{y}}}{{\text{Zn}}}_{1-{\text{y}}}{\text{O}}\). Intrinsic gate delay, the percentage decrement is ~ 54.15 and ~ 59.95% for \({{\text{Mg}}}_{{\text{y}}}{{\text{Zn}}}_{1-{\text{y}}}{\text{O}}\) and \({{\text{Cd}}}_{{\text{x}}}{{\text{Zn}}}_{1-{\text{x}}}{\text{O}}\) respectively w.r.t ZnO. Both the \({{\text{Cd}}}_{{\text{x}}}{{\text{Zn}}}_{1-{\text{x}}}{\text{O}}\) and \({{\text{Mg}}}_{{\text{y}}}{{\text{Zn}}}_{1-{\text{y}}}{\text{O}}\) TFT shows unanimous decrease in delay for the resistive inverter as well as AMLCD pixel display circuits. The reported results shows that bottom gate \({{\text{Cd}}}_{{\text{x}}}{{\text{Zn}}}_{1-{\text{x}}}{\text{O}}\) TFT has better performance for above-mentioned performance parameters. The numerical simulations are performed on Silvaco ATLAS TCAD simulator.Please confirm if the author names are presented accurately and in the correct sequence (given name, middle name/initial, family name). Author 1 Given name: [Binay Binod] Last name [Kumar], Author 3 Given name: [Pramod Kumar] Last name [Tiwari], Author 4 Given name: [Aniruddh Bahadur] Last name [Yadav]. Also, kindly confirm the details in the metadata are correctYes, the sequence of authors is correct and the details in the metadata is also accurate. Journal instruction requires a city and country for affiliations; however, these are missing in affiliation [1, 2, 4]. Please verify if the provided city is correct and amend if necessary.We apologize for the misunderstanding. However, the city and country names are already correctly mentioned in Affiliation [1, 2 and 4].

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Authors and Affiliations

  1. Solid State Electronics and VLSI Lab, Department of ECE, NIT Jamshedpur, Jamshedpur, Jharkhand, India

    Binay Binod Kumar, Shubham Kumar & Kunal Singh

  2. Department of Electrical Engineering, Indian Institute of Technology Patna, Patna, India

    Pramod Kumar Tiwari

  3. Department of ECE, Velagapudi Ramakrishna Siddhartha Engineering College, Vijayawada, Andhra Pradesh, India

    Aniruddh Bahadur Yadav

  4. Department of Physics, L.N.D. College Motihari (B.R. Ambedkar Bihar University), Motihari, Bihar, India

    Sarvesh Dubey

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Contributions

BBK carried out TCAD simulation reported in paper, addressed the reviewer comments and revised the manuscript as per the directions. SK carried out TCAD simulation reported in paper, made graphs, written manuscript. Dr. PKT final draft of manuscript. Dr. ABY grammatical correction and some calibration work. Dr. SD grammatical correction and some calibration work. Dr. KS final draft of manuscript check and made graphs.

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Correspondence to Kunal Singh.

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Kumar, B.B., Kumar, S., Tiwari, P.K. et al. Performance Investigation of Bottom Gate ZnO Based TFT for High-Speed Digital Display Circuit Applications. Trans. Electr. Electron. Mater. 25, 314–326 (2024). https://doi.org/10.1007/s42341-024-00515-6

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