Skip to main content
SpringerLink
Log in

Impact of Back Gate Bias on Analog Performance of Dopingless Transistor

  • Regular Paper
  • Published:
Transactions on Electrical and Electronic Materials Aims and scope Submit manuscript

Abstract

In this brief, the impact of back gate bias \((V_{gb})\), on analog performance of silicon on insulator dopingless transistor (SOI-DLT) is investigated. It is observed that SOI-DLTs are more immune to \(V_{gb}\) in contrast to its conventional counterpart SOI junctionless transistor (SOI-JLT). When \(V_{gb}\) is increased from − 1.5 V to 1.5 V, the variation in transconductance \((g_m)\) and intrinsic gain (\(g_mr_O\)) of SOI-JLT is 1.3 and 21.4 times higher than SOI-DLT. The insignificant variation is observed in \(g_m\) and \(g_mr_O\) of SOI-DLT against \(V_{gb}\) than SOI-JLT due to the use of lightly doped channel. Further, the device reliability of SOI-DLT against impact ionization is evaluated by measuring the electron concentration and electric field near the drain side. We have found that the SOI-DLT is less sensitive to impact ionization in comparison to conventional SOI-JLT. Hence, the simulation results shown in this paper offer an opportunity for future analog integrated circuits designing with SOI-DLT structure under the influence of \(V_{gb}\).

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

Data Availability

All data and materials as well as software application or custom code support our published claims and comply with field standards.

References

  1. J.-W. Han, J. Kim, M. Meyyappan, Transformable Junctionless Transistor (T-JLT). IEEE Trans. Electron Devices 67(6), 2639–2644 (2020). https://doi.org/10.1109/TED.2020.2988443

    Article  CAS  Google Scholar 

  2. U. Khan, B. Ghosh, M.W. Akram, A. Salimath, A comparative study of SELBOX-JLT and SOI-JLT. Appl. Phys. A Mater. Sci. Process. 117, 2281–2288 (2014). https://doi.org/10.1007/s00339-014-8661-3

    Article  CAS  Google Scholar 

  3. N. Kamal, M. Panchore, J. Singh, 3-D simulation of junction- and doping-free field-effect transistor under heavy ion irradiation. IEEE Trans. Device Mater. Reliab. 18(2), 173–179 (2018). https://doi.org/10.1109/TDMR.2018.2811493

    Article  CAS  Google Scholar 

  4. M. Ehteshamuddin, S.A. Loan, M. Rafat, Planar junctionless silicon-on-insulator transistor with buried metal layer. IEEE Electron Device Lett. 39(6), 799–802 (2018). https://doi.org/10.1109/LED.2018.2829915

    Article  CAS  Google Scholar 

  5. T. Ohrou, N. Sugii, T. Hiramoto, Impact of parameter variations and random dopant fluctuations on short-channel fully depleted SOI MOSFETs with extremely thin BOX. IEEE Electron Device Lett. 28(8), 740–742 (2007). https://doi.org/10.1109/LED.2007.901276

    Article  CAS  Google Scholar 

  6. R. Trevisoli, R. Trevisoli Doria, M. de Souza, M.A. Pavanello, Substrate bias influence on the operation of junctionless nanowire transistors. IEEE Trans. Electron Devices 61(5), 1575–1582 (2014). https://doi.org/10.1109/TED.2014.2309334

    Article  CAS  Google Scholar 

  7. Dae-Young. Jeon, Mireille Mouis, Sylvain Barraud, Gérard. Ghibaudo, Controlling the effective channel thickness of junctionless transistors by substrate bias. IEEE Trans. Electron Devices 67(11), 4736–4740 (2020). https://doi.org/10.1109/TED.2020.3020284

    Article  CAS  Google Scholar 

  8. Dae-Young. Jeon, Mireille Mouis, Sylvain Barraud, Gérard. Ghibaudo, Impact of channel length on the Operation of junctionless transistors with substrate biasing. IEEE Trans. Electron Devices 68(06), 4736–4740 (2021). https://doi.org/10.1109/TED.2021.3069936

    Article  Google Scholar 

  9. S.J. Park, D.-Y. Jeon, L. Montès, S. Barraud, G.-T. Kim, G. Ghibaudo, Impact of channel width on back biasing effect in trigate MOSFET. Microelectron. Eng. 114, 91–97 (2014). https://doi.org/10.1016/j.mee.2013.09.016

    Article  CAS  Google Scholar 

  10. S.J. Park, D.-Y. Jeon, L. Montès, S. Barraud, G.-T. Kim, G. Ghibaudo, Back biasing effects in tri-gate junctionless transistors. Solid-State Electron. 87, 74–79 (2013). https://doi.org/10.1016/j.sse.2013.06.004

    Article  CAS  Google Scholar 

  11. Bhaskar Awadhiya, Sameer Yadav, Pranshoo Upadhyay, Pravin N. Kondekar, Effect of back gate biasing in negative capacitance field effect transistor. Micro Nanostruct. 166, 207226 (2022). https://doi.org/10.1016/j.micrna.2022.207226

    Article  CAS  Google Scholar 

  12. B. Awadhiya, S. Yadav, A. Acharya, Interface trap charges analysis on DC and high frequency characteristics of UTBB-FDSOI FET. Silicon (2022). https://doi.org/10.1007/s12633-022-02053-3

    Article  Google Scholar 

  13. F. Jand, J.M. Sallese, Modeling nanowire and double-gate junctionless field-effect transistors (Cambridge University Press, Cambridge, 2018), pp.1–14

    Google Scholar 

  14. A. Veloso, A. Veloso, P. Matagne, E. Simoen, B. Kaczer, G. Eneman, H. Mertens, D. Yakimets, B. Parvais, D. Mocuta, Junctionless versus inversion-mode lateral semiconductor nanowire transistors. J. Phys. Condens. Matter (2018). https://doi.org/10.1088/1361-648X/aad7c7

    Article  Google Scholar 

  15. Seung Min Lee and Jong Tae Park, The impact of substrate bias on the steep subthreshold slope in junctionless MuGFETs. IEEE Trans. Electron Devices 60(11), 3856–3861 (2013). https://doi.org/10.1109/TED.2013.2280275

    Article  CAS  Google Scholar 

  16. N. Kamal, A. Lahgere, J. Singh, Evaluation of radiation resiliency on emerging junctionless/dopingless devices and circuits. IEEE Trans. Device Mater. Reliab. 19(4), 728–732 (2019). https://doi.org/10.1109/TDMR.2019.2949064

    Article  CAS  Google Scholar 

  17. S. Singh, P.N. Kondekar, Dopingless super-steep impact ionisation MOS (dopingless-IMOS) based on work-function engineering. Electron. Lett. 50(12), 888–889 (2014). https://doi.org/10.1049/el.2014.1072

    Article  CAS  Google Scholar 

  18. C. Sahu, J. Singh, Potential benefits and sensitivity analysis of dopingless transistor for low power applications. IEEE Trans. Electron Devices 62(3), 729–735 (2015). https://doi.org/10.1109/TED.2015.2389900

    Article  CAS  Google Scholar 

  19. C. Sahu, J. Singh, Charge-plasma based process variation immune junctionless transistor. IEEE Electron Device Lett. 35(3), 411–413 (2014). https://doi.org/10.1109/LED.2013.2297451

    Article  CAS  Google Scholar 

  20. Meena Panchore, Jawar Singh, Saraju P. Mohanty, Impact of channel hot carrier effect in junction and doping-free devices and circuits. IEEE Trans. Electron Devices 63(12), 5068–5071 (2016). https://doi.org/10.1109/TED.2016.2619621

    Article  Google Scholar 

  21. Meena Panchore, Lokesh Bramhane, Jawar Singh, Channel hot carrier degradation in the channel of junctionless transistors: a device-and circuit-level perspective. J. Comput. Electron. 20, 1196–1201 (2021). https://doi.org/10.1007/s10825-021-01688-6

    Article  CAS  Google Scholar 

  22. R. Taco, I. Levi, A. Fish and M. Lanuzza, Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design, in IEEE 28th Convention of Electrical & Electronics Engineers in Israel, (2014) pp. 1-4, https://doi.org/10.1109/EEEI.2014.7005822.

  23. L. Grenouillet et al., UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below, in International Electron Devices Meeting (2012) pp. 3.6.1-3.6.4, https://doi.org/10.1109/IEDM.2012.6478974.

  24. Y. Sahu, P. Kushwaha, A. Dasgupta, C. Hu, Y.S. Chauhan, Compact modeling of drain current thermal noise in FDSOI MOSFETs including back-bias effect. IEEE Trans. Microw. Theory Tech. 65(7), 2261–2270 (2017). https://doi.org/10.1109/TMTT.2017.2666811

    Article  Google Scholar 

  25. P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J.P. Duarte, C. Hu, Y.S. Chauhan, Modeling the impact of substrate depletion in FDSOI MOSFETs’. Solid-State Electron. 104(7), 6–11 (2015). https://doi.org/10.1016/j.sse.2014.11.002

    Article  CAS  Google Scholar 

  26. K. Gopalakrishnan, P.B. Griffin, J.D. Plummer, Impact ionization MOS (I-MOS)-Part I: device and circuit simulations. IEEE Trans. Electron Devices 52(1), 69–76 (2005). https://doi.org/10.1109/TED.2004.841344

    Article  CAS  Google Scholar 

  27. K. Gopalakrishnan, R. Woo, C. Jungemann, P.B. Griffin, J.D. Plummer, Impact ionization MOS (I-MOS)-Part II: experimental results. IEEE Trans. Electron Devices 52(1), 77–84 (2005). https://doi.org/10.1109/TED.2004.841345

    Article  CAS  Google Scholar 

  28. R.V. Overstraeten, H. De Man, Measurement of the ionization rates in diffused silicon p-n junctions. Solid State Electron. 13(5), 583–608 (1970). https://doi.org/10.1016/0038-1101(70)90139-5

    Article  Google Scholar 

  29. A. Islam, K. Kalna, Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: \(Si/SiO_2\) interface charges and quantum mechanical effects. IOP Conf. Ser. Mater. Sci. Eng. 504, 012021 (2019). https://doi.org/10.1088/1757-899X/504/1/012021

    Article  CAS  Google Scholar 

  30. ATLAS Users manual, Version 5.2.8.R (2019)

Download references

Funding

No funding was received to assist with the preparation of this manuscript.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Patna, Bihar, 800005, India

    Rakesh Kumar & Meena Panchore

Authors
  1. Rakesh Kumar
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Meena Panchore
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Meena Panchore.

Ethics declarations

Conflict of interest

The Authors declare that they have no conflict of interest.

Consent for Publication

We agree to the terms and policies for the publication of the articles.

Consent to Participate

We agree to the terms and policies for the publication of the articles.

Ethical Approval

Accepted principles of ethical and professional conduct have been followed. No human or animals participation involved in the research.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Kumar, R., Panchore, M. Impact of Back Gate Bias on Analog Performance of Dopingless Transistor. Trans. Electr. Electron. Mater. 24, 115–121 (2023). https://doi.org/10.1007/s42341-022-00426-4

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s42341-022-00426-4

Keywords

Search

Navigation