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Effects of Hafnium Oxide on Surface Potential and Drain Current Models for Subthreshold Short Channel Metal–Oxide–Semiconductor-Field-Effect-Transistor

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Abstract

Surface potential and drain current models for a physically based double halo metal–oxide–semiconductor-field-effect-transistor (MOSFET) are reported. The proposed models have been established in sub-threshold mode of MOSFET operation. The depletion layer depth used in the pseudo two dimensional Poisson’s equation comprises the effect of two symmetrical pocket implantations at both the ends of the channel region. In this effort, improvement in the investigation is brought in by taking lateral asymmetric channel owing to non-uniform doping. The conventional silicon-dioxide (SiO2) material is replaced with a promising high-k dielectric material hafnium oxide (HfO2) to analyze the surface potential and drain current models. Analytical results have been compared using Synopsys technology computer aided design (TCAD). Excellent conformities between the analytical models and simulations are observed.

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References

  1. K. Joardar, K.K. Gullapalli, C.C. McAndrew, M.E. Burnham, A. Wild, An improved MOSFET model for circuit simulation. IEEE Trans. Electron Devices 45, 134–148 (1998)

    Article  Google Scholar 

  2. G. Gildenblat, X. Li, W. Wu, H. Wang, A. Jha, R. Van Langevelde, G.D.J. Smit, A.J. Scholten, D.B.M. Klaassen, PSP: an advanced surface-potential based MOSFET model for circuit simulation. IEEE Trans. Electron Devices 53, 1979–1993 (2006)

    Article  CAS  Google Scholar 

  3. H. Chakrabarti, R. Maity, N. P. Maity, Analysis of surface potential for dual-material-double-gate MOSFET based on modeling and simulation. Microsyst. Technol. (2019). https://doi.org/10.1007/s00542-019-04386-3

    Article  Google Scholar 

  4. R.V. Langevelde, F.M. Klassen, An explicit Surface-potential-based MOSFET model for circuit simulation. Solid State Electron. 44, 409–418 (2000)

    Article  Google Scholar 

  5. T.L. Chen, G. Gildenblat, An extended analytical approximation for the MOSFET surface potential. Solid State Electron. 49, 267–270 (2005)

    Article  CAS  Google Scholar 

  6. A.R. Boothroyd, S.W. Tarasewicz, C. Slaby, MISNAN: a physically based continuous MOSFET model for CAD applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10, 1512–1529 (1991)

    Article  Google Scholar 

  7. M.M. Mattausch, U. Feldmann, A. Rahm, M. Bolu, D. Savignac, Unified complete MOSFET model for analysis of digital and analog circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 15, 1–7 (1996)

    Article  Google Scholar 

  8. S. Roy, A. Chatterjee, D.K. Sinha, R. Pirogova, S. Baishya, 2-D analytical modeling of surface potential and threshold voltage for vertical super-thin body FET. IEEE Trans. Electron Devices 64, 2106–2112 (1017)

    Article  Google Scholar 

  9. N. Sadachika, D. Kitamaru, Y. Uetsuji, D. Navarro, M.M. Yusoff, T. Ezaki, H.J. Mattausch, M.M. Mattausch, Completely surface-potential based compact model of the fully depleted SOI MOSFET including short channel effects. IEEE Trans. Electron Devices 53, 2017–2024 (2006)

    Article  CAS  Google Scholar 

  10. R. Saha, S. Baishya, B. Bhowmick, 3D Analytical model of surface potential, threshold voltage, and subthreshold swing in dual material gate (DMG) SOI FinFETs. J. Comput. Electron. 17, 153–162 (2018)

    Article  CAS  Google Scholar 

  11. V. Narender, K.A. Gridhardas, Surface potential modeling of graded channel gate stack (GCGS) high-k dielectric dual material double gate (DMDG) MOSFET and analog/RF performance study. Silicon 10, 2865–2875 (2018)

    Article  Google Scholar 

  12. B.H. Calhoun, A.P. Chandrakasan, Static noise margin variation for subthreshold SRAM in 65-nm CMOS. IEEE J. Solid-State Circuits 41, 1673–1679 (2006)

    Article  Google Scholar 

  13. B.C. Paul, A. Raychowdhury, K. Roy, Device optimization for digital subthreshold logic operation. IEEE Trans. Electron Devices 52, 237–247 (2005)

    Article  CAS  Google Scholar 

  14. S. Chakraborty, A. Mallik, C.K. Sarkar, Impact on halo dopingon the subthreshold performance of deep sub micrometer CMOS devices and circuits for ultralow power analog/mixed signal applications. IEEE Trans. Electron Devices 54, 241–248 (2007)

    Article  Google Scholar 

  15. A. Wang, A. Chandrakasan, A 180-mV subthreshold FFT processor using a minimum energy design methodology. IEEE J. Solid-State Circuits 40, 310–319 (2005)

    Article  Google Scholar 

  16. Y. Taur, D.A. Buchanan, W. Chen, D.J. Frank, K.E. Ismail, S.-H. Lo, G.A. Sai-Halasz, R.G. Viswanathan, H.-J.C. Wann, S.J. Wind, H.-S. Wong, CMOS scaling into the nanometer regime. Proc. IEEE 85, 486–504 (1997)

    Article  Google Scholar 

  17. R. Gwoziecki, T. Skotnicki, Smart pockets: total suppression of roll-off and rollup, in IEEE Symposium on VLSI Technology (1999), pp. 91–92

  18. H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiai, T. Mogami, T. Kunio, Sub 50-nm physical gate length CMOS technology and beyond using steep halo. IEEE Trans. Electron Devices 49, 89–95 (2002)

    Article  CAS  Google Scholar 

  19. K. Liu, J. Wu, J. Chen, A. Jain, Fluorine-assisted super halo for sub-50 nm transistors. IEEE Electron Device Lett. 24, 180–182 (2003)

    Article  CAS  Google Scholar 

  20. A. Hori, A. Hiroki, H. Nakaoka, M. Segawa, T. Hori, Quarter-micrometer SPI (self-aligned pocket implantation) MOSFET’s and its application for low supply voltage operation. IEEE Trans. Electron Devices 42, 78–86 (1995)

    Article  CAS  Google Scholar 

  21. A. Hori, M. Segawa, H. Shimomura, S. Kameyama, A self aligned pocket implantation (SPI) technology for 0.2-mu m dual gate CMOS. IEEE Electron Device Lett. 13, 174–176 (1992)

    Article  Google Scholar 

  22. X. Chen, H. Zhao, Y. Xiong, F. Wei, H.J. Du, Z. Tang, B. Tang, J. Yan, Study of Hf–Ti–O thin film as high-k gate dielectric and application for ETSOI MOSFETs. J. Electron. Mater. 45, 4407–4411 (2016)

    Article  CAS  Google Scholar 

  23. N.P. Maity, R. Maity, S. Baishya, A tunneling current model with a realistic barrier for ultra thin high-k dielectric ZrO2 material based MOS devices. Silicon 10, 1645–1652 (2018)

    Article  CAS  Google Scholar 

  24. Y. Swami, S. Rai, Ultra thin high-k dielectric profile based NBTI compact model for nanoscale bulk MOSFET. Silicon 11, 1661–1671 (2019)

    Article  CAS  Google Scholar 

  25. P. Banerjee, S.K. Sarkar, Modeling and analysis of a front high-k gate stack dual-material tri-gate Schottky barrier silicon-on-insulator MOSFET with a dual-material bottom gate. Silicon 11, 513–519 (2019)

    Article  CAS  Google Scholar 

  26. N.P. Maity, R. Maity, R. Thapa, S. Baishya, A tunneling current density model for ultra thin HfO2 high-k dielectric material based MOS devices. Supperlattices Microstruct. 95, 24–32 (2016)

    Article  CAS  Google Scholar 

  27. N.P. Maity, R. Maity, S. Baishya, Voltage and oxide thickness dependent tunneling current density and tunnel resistivity model: application to high-k material HfO2 based MOS devices. Supperlattices Microstruct. 111, 628–641 (2017)

    Article  CAS  Google Scholar 

  28. R. Basak, B. Maiti, A. Mallik, Analytical model of gate leakage current through bilayer oxide stack in advanced MOSFET. Supperlattices Microstruct. 80, 20–31 (2015)

    Article  CAS  Google Scholar 

  29. N.P. Maity, R. Maity, S. Baishya, An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET. J. Comput. Electron. 18, 65–75 (2019)

    Article  CAS  Google Scholar 

  30. N. P. Maity, A. Pandeya, S. Chakraborty, M. Roy, High-k HfO2 based metal-oxide-semiconductor devices using silicon and silicon carbide semiconductor. J. Nano Electron. Phys. 4, 948–956 (2012)

    Google Scholar 

  31. N.P. Maity, R. Maity, S. Maity, S. Baishya, Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation. J. Comput. Electron. 18, 492–499 (2019)

    Article  CAS  Google Scholar 

  32. N.P. Maity, A. Pandeya, S. Chakraborty, M. Roy, High-k HfO2 based metal-oxide-semiconductor devices using silicon and silicon carbide semiconductor. J. Nano-Electron. Phys. 4, 948–956 (2012)

    Google Scholar 

  33. K.W. Terrill, C. Hu, P.K. Ko, An analytical model for the channel electric field in MOSFETs with graded-drain structure. IEEE Electron Device Lett. 5, 440–442 (1984)

    Article  Google Scholar 

  34. C.S. Ho, J.J. Liou, K. Huang, C. Cheng, An analytical subthreshold current model for pocket implanted NMOSFETs. IEEE Trans. Electron Devices 50, 1475–1479 (2003)

    Article  CAS  Google Scholar 

  35. Y.-S. Pang, J.R. Brews, Analytical subthreshold surface potential model for pocket n-MOSFETs. IEEE Trans. Electron Devices 49, 2209–2216 (2002)

    Article  Google Scholar 

  36. Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P.K. Ko, Y.C. Cheng, Threshold voltage for deep submicrometer MOSFETs. IEEE Trans. Electron Devices 40, 86–95 (1993)

    Article  Google Scholar 

  37. B. Yu, C.H.J. Wann, E.D. Nowak, K. Noda, C. Hu, Short-channel effect by lateral channel engineering in deep-submicrometer MOSFET’s. IEEE Trans. Electron Devices 44, 627–634 (1997)

    Article  CAS  Google Scholar 

  38. Y.A. El-Mansy, A.R. Boothroyd, A simple 2-D model for IGFET operation in saturation region. IEEE Trans. Electron Devices 24, 254–262 (1977)

    Article  Google Scholar 

  39. S. Baishya, A. Mallik, C.K. Sarkar, A subthreshold surface potential model fro short channel MOSFET taking into account the varying depth of channel depletion layer due to source and drain junction. IEEE Trans. Electron Devices 53, 507–514 (2006)

    Article  Google Scholar 

  40. S. Baishya, A. Mallik, C.K. Sarkar, Subthreshold surface potential and drain current models for short channel pocket-implanted MOSFETs. Microelectron. Eng. 84, 653–662 (2007)

    Article  CAS  Google Scholar 

  41. T.A. Fjeldly, M. Shur, Threshold voltage modeling and the subthreshold regime of operation of short channel MOSFETs. IEEE Trans. Electron Devices 40, 137–145 (1993)

    Article  Google Scholar 

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Acknowledgements

The authors would like to thank and highly indebted to TCAD Laboratory, National Institute of Technology, Silchar, India for supporting this technical work.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Mizoram University (A Central University), Aizawl, 796 004, India

    N. P. Maity & Reshmi Maity

  2. Department of Electrical Engineering, Mizoram University (A Central University), Aizawl, 796 004, India

    Subir Dutta & Subhasish Deb

  3. Department of Electronics and Communication Engineering, K. L. University, Gunter, Vaddeswaram, 522 502, India

    K. Girija Sravani & K. Srinivasa Rao

  4. Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, 788 010, India

    S. Baishya

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  1. N. P. Maity
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Maity, N.P., Maity, R., Dutta, S. et al. Effects of Hafnium Oxide on Surface Potential and Drain Current Models for Subthreshold Short Channel Metal–Oxide–Semiconductor-Field-Effect-Transistor. Trans. Electr. Electron. Mater. 21, 339–347 (2020). https://doi.org/10.1007/s42341-020-00181-4

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