1 Introduction

Recently, various radar systems have been designed to detect target velocity [1,2,3,4,5], but they all have weaknesses in many requirements. In [1], the authors decided that the stationary or multiple targets can be detected and false alarm detection may occur. Detection of targets at distance greater than 5 m is difficult compared with other radars and consequently, their angular resolution is poor [2]. There are problems when detecting a target in dark or in presence of obstacles and high-performance hardware is required for system computations and data extraction [3]. Lidar radar is extremely expensive compared with other applications and susceptibility to weather conditions [4]. In [5], design and implementation of radar signal processing using FPGA is applied in Linear Frequency Modulated Continuous Wave Radar (LFMCW) radar based on adaptive threshold but the complexity is high according to the complexity of compressive sensing due to target information extraction such as range and velocity. Other applications that use the radar sensors in industrial machinery, drones, automobiles [6, 7]

Also, in [8] target classification and estimating movement direction with accuracy of 85%. In addition, the authors in [9] integrate both the transmitter/ receiver circuit with the radar antenna to reduce the radar size.

Radar can be classified into two main parts; pulsed and CW, the latter is simple to implement and has received increasing attention [10]. The velocity of the target can be extracted from the received data after signal processing, also the target range can be determined, according to the radar objectives, after modulating in the frequency of the transmitted signals. Target velocity and range can be evaluated using two-dimensional (2D) Fast Fourier Transform (FFT) in both range and azimuth directions [11]. Radar signal has been processed for target detection and classifications as illustrated in [12,13,14].

Nowadays, FMCW radars are often called “radars of the future” due to achievement an extremely high degree of range resolution making the radar less susceptible to interfering clutter and also Low Probability of Interception (LPI). It is usually in S band or L band that the industry still uses chirp pulse radars, because of the need for long ranges. FMCW radars, unfortunately, do not have long ranges. FMCW radars find widespread usage in military applications and marine navigation due to their stealth properties, allowing them to see without being seen and giving away their location to radar interceptors [15].

In the present work, target velocity only can be extracted from the received radar signals using Doppler filter bank which is designed according to the range of measured velocities. The suggested approach can resolve many problems that appear in the previous related works. Also, image processing can be added in the algorithm if the vehicle plate is required according to the police radar speed in the main highway. The organization of this paper is planned as follows; after the introduction, Sect. 2 gives a survey on the continuous wave radar. Section 3 focuses on the methods of target speed detection. Hardware implementation of the proposed design is presented in Sect. 4. Real-time implementation and experimental results are presented in Sect. 5. Finally, the conclusion comes in Sect. 6.

1.1 Continuous wave radar review

The main function of CW radar system is measuring target speed. However, it does not provide any range (distance) information unless a modulation in frequency is required to perform this matter. The speed can be determined using frequency difference between the transmitted and received signal frequencies which is called Doppler frequency.

Radar motion sensors are based on the same principle, but they must also be capable of detecting slow changes in the received field strength due to variable interference conditions that may exist.

Continuous Wave (CW) radar has several advantages over other radar systems such as: simplicity, low-cost effective, small size, low power consumption, and Doppler capability [16]. According to Fig. 1 which represents the general block diagram of CW radar system, the receiver declares detection at a certain Doppler pin if the output passes through the detection threshold in the detector block. Narrow Filter Bank (NFB) is used after the digital detector output which consists of many filters’ frequency ranges. The length of such blocks is normally referred to as the dwell interval, integration time, or coherent processing interval. The dwell interval determines the frequency resolution or the bandwidth of the individual NBFs.

Fig. 1
figure 1

General block diagram of CW radar system [16]

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If the range of the detected target is called “R”, the total distance between the radar and target in a two-way communication path will be 2R. Then, the total angle of excursion made by the electromagnetic wave during the two-way communication path between the Radar and target will be equal to 4πR/λ radians. Where λ is one wave length.

The relation between the angular frequency, w, and phase angle, Φ, is given by:

$$w=\frac{d\varnothing }{dt}=2\pi f$$
(1)

where, f is the signal frequency, that Eq. (1) can be written as:

$$f=\frac{1}{2\pi }\frac{d{\varnothing }}{dt}$$
(2)

Substitute, the phase angle by 4πR/λ in Eq. (2), so the Doppler frequency, \({f}_{d}\), can be written as:

$${f}_{d}=\frac{1}{2\pi }\frac{d (\frac{4{\pi R}}{\uplambda })}{dt}$$
$${f}_{d}=\frac{1}{2\pi }\frac{4\pi }{\uplambda }\frac{d (\text{R})}{dt}$$
$${f}_{d}=\frac{2{V}_{r}}{\uplambda }$$
(3)

where Vr is the target speed. The CW radar equation can now be determined according to the following equation:

$$SNR=\frac{{P}_{av}T{G}_{r}{G}_{t}{\lambda }^{2}\sigma }{{(4\pi )}^{3}{R}^{4}K{T}_{o}FL}$$
(4)

where \({P}_{av}\) is the average power transmitted by the radar system, T is the time duration, \({G}_{r}\) is the receiver antenna gain, \({G}_{t}\) is the transmitted antenna gain, \(\sigma\) is the radar cross-section, \(K\) is the Boltzman constant, \({T}_{o}\) is the room temperature, \(F\) is the system noise figure, and L is the system losses.

1.2 Target speed detection

In FMCW radar, the transmitted waveform can be either triangular or sawtooth to extract the target information. But sawtooth transmission waveforms are commonly used in many radar systems. The frequency of the sawtooth waveform is defined by Eq. (5).

$$f\left(t\right)={f}_{c}+\frac{B}{T}t$$
(5)

where fc is the carrier frequency; B is the bandwidth; and T is the period. For simplicity, replace B/T by α, and consequently the instantaneous phase, \(\varphi \left(t\right),\) of the transmitted signal can be obtained by integrating the transmitted signal frequency with respect to time t, as illustrated in Eq. (6).

$$\varphi \left(t\right)=2\pi {\int }_{0}^{t}f\left(t\right)dt=2\pi {\int }_{0}^{t}({f}_{c}+\alpha t)dt$$
$$\varphi \left(t\right)=2\pi ({f}_{c}t+\frac{\alpha {t}^{2}}{2})$$
(6)

The transmitted signal, STx(t), with initial phase, \({\varphi }_{o}\), and amplitude, A, can be obtained according to Eq. (7).

$${S}_{Tx}\left(t\right)=A\text{cos}(2\pi \left({f}_{c}t+\frac{\alpha {t}^{2}}{2}\right)+{\varphi }_{o})$$
(7)

The received signal, SRx(t), can be expressed after a certain time delay as in Eq. (8)

$${S}_{Rx}\left(t\right)=B\text{cos}(2\pi \left({f}_{c}(t-\tau )+\frac{\alpha {(t-\tau )}^{2}}{2}\right)+{\varphi }_{o})$$
(8)

where B is the received signal amplitude, and τ is expressed as

$$\tau =\frac{2(R+\nu t)}{c}$$
(9)

Here, C is the speed of light.

Figure 2 shows the block diagram of the FMCW radar signal processing based on FFT in range and Doppler directions.

Fig. 2
figure 2

Block diagram of CW radar signal processing based on FFT in range and Doppler directions

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Figure 3 represents a block diagram of radar signal processing for target speed detection based on filter bank. The received beat signal is digitized using Analog-to-Digital (ADC) converter. Window can be used if clutter or unwanted signals are joint to the useful signals with high side lobe levels.

Fig. 3
figure 3

Block diagram of the proposed radar signal processing based on filter bank

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1.3 Hardware Architecture of the proposed design

The proposed signal processor algorithm of CW radar system based on filter bank is implemented using FPGA kit. The usage of FPGA in signal processing has many advantages where it consists of many blocks are composed of lookup tables (LUTs) and flip-flops that can be programmed to implement complex logic functions and algorithms. Also, the interconnects provide pathways for routing signals between different logic blocks, allowing for flexible connectivity. The used FPGA contains many functions that can realize the signal processing algorithms such as: Programmable input/output (I/O) unit, basic programmable logic unit, embedded RAM, abundant wiring resources, bottom embedded functional unit, and embedded dedicated hard core. The used FPGA consists of UltraScale Kintex + platform using the Vivado Xilinx tool. A flow chart describing the process of the signal processor using FPGA to detect the target speed as illustrated in Fig. 4.

Fig.4
figure 4

Flow chart of FPGA process for CW signal processor

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The received radar signal is applied to the bank of filters through the used FPGA kit. The bandwidth of each filter is designed according to the specific target speed as shown in Table 1. The response of each filter is obtained which consequently represents nearly the target speed. Once the target speed information has been extracted from the analyzed output filter response, it can be utilized for further processing or display, depending on the specific requirements. This information may be employed in subsequent stages of the signal processing pipeline or presented in a user-friendly format.

Table 1 Relation between target speed and filter bank frequencies
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According to the filter bank effect, the target speed can be determined according to the bandwidth of the specific filter. In the proposed signal processor, the filter bank is divided into 6 filters with different bandwidths as shown in the above table. The target speed range is considered from 50 km/hr till 100 km/hr which can be changed according to the filter bandwidth.

The hardware implementation of the proposed processor is mainly divided into three stages; first one is the verification of the received signal using FPGA [17, 18], second stage is the verification and implementation of the filter bank specifications, and the third stage is the target speed calculations and display the result.

First stage: The received signal is digitized using ADC converter and then analyzed and verified using FPGA as shown in Fig. 5.

Fig. 5
figure 5

The received signal verification using FPGA

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Second stage: According to Table 1 which specifies the bandwidth of the designed filters, there are six filters with different bandwidths dependent on the corresponding target speed; low pass filter with cutoff frequency at 1 MHz, band pass filter with bandwidth form 1 MHz to 5 MHz, band pass filter with bandwidth form 6 MHz to 10 MHz, band pass filter with bandwidth form 11 MHz to 15 MHz, band pass filter with bandwidth form 16 MHz to 20 MHz, and high pass filter with cutoff frequency at 20 MHz as shown in Fig. 6.

Fig.6
figure 6

Block diagram of filter bank implementation using FPGA

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1.4 Real-time implementation and Results

The filter specifications in the bank are verified using both MATLAB and Vivado as shown in Fig. 7 and Fig. 8 respectively [19, 20].

Fig.7
figure 7

Design of band pass filter with bandwidth from 6 to 10 MHz using Matlab

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Fig.8
figure 8

Design of band pass filter with bandwidth from 6 to 10 MHz using Vivado

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Third stage: Target speed can be determined according to the doppler frequency of the received radar signal which extracted from the filter bank using FPGA as shown in Fig. 9.

Fig.9
figure 9

General Block diagram of the target speed detector using FPGA

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The output response of each filter leads to a certain speed according to Table 1 within an accuracy of 1 MHz for every 2 km/hr target speed. This accuracy can be modified according to the processor design of the filter bank. The response of any filter can be tested using FPGA as illustrated in Fig. 10. The response of filter number 3 which indicates to target speed of 70 km/hr. From this figure, it is clear that, the output response of any filter can be used to calculate the target speed correctly (Table 2).

Fig.10
figure 10

Target speed detector of band pass filter (70 km/hr) using FPGA

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Table 2 Comparison of the proposed radar processor with another radar processor
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1.5 Real-Time implementation and experimental results

The real-experiment includes hardware components and software programming using FPGA. The hardware components are FPGA signal processor kit, ADC and DAC for analog and digital signal interface, power spectrum analyzer, digital oscilloscope, and LCD display. The experiment setup is illustrated in Fig. 11.

Fig.11
figure 11

Real-time setup of the proposed signal processor

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Figure 12 represents target speed detection at velocity 80 km/hr as illustrates on digital oscilloscope. The response of digital filter associated with this speed at 13 MHz is measured and tested as shown in Fig. 13. The measured target speed is then appeared on LCD display to ensure the accurate speed as shown in Fig. 14.

Fig.12
figure 12

Target speed detection at velocity of 80 km/hr using digital oscilloscope

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Fig.13
figure 13

Filter response at 13 MHz (speed of 80 km/hr) using spectrum analyzer

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Fig.14
figure 14

Target speed indicator after processing using LCD display

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According to these results from the real experiment, it is clear that, the target speed can be detected and measured using low- cost components and with suitable accurate according to the design parameters of doppler filter bank.

From this comparison, it is clear that, the proposed radar processor has lower complexity compared with the other radar processor and any modifications can be achieved on the proposed algorithm to enhance the output detection with keeping lower complexity.

2 Conclusion

This study describes the design of a low-cost CW radar signal processor that uses FPGA technology to determine vehicle speed. In addition to using FPGA, the system is scalable and flexible, which makes it easy to modify for improvements and optimizations down the road.

A Doppler filter bank is constructed with bandwidths corresponding to the upper limit of the vehicle's speed range thanks to programming in the FPGA. Every filter response is connected to the desired speed based on user-controlled accuracy. The usability of the radar signal processor is further improved by integrating it with a Raspberry Pi and a monitor, which offers a user-friendly interface for visualizing and presenting the velocity of the discovered targets.

This hardware configuration enables a small and affordable radar system that may be used for several tasks, including object tracking, speed measurement, and traffic monitoring. As technology advances, it will be possible to improve the radar system, including range detection capabilities. Pulse compression approach can be added or any processing algorithms, including time-of-flight measurements. In addition to velocity detection, precise target range information can be acquired by incorporating these techniques into the radar system. In the future, this technique can be changed to employ the FFT algorithm for precise target speed measurement. Along with a high-quality camera, image processing can be added to this technique for more applications using the same hardware.

Finally, the parameters of the signal processor are adjusted for optimal performance based on the Doppler filter bank bandwidths and the range of vehicle velocities. As various scenarios are applied in real time, the radar settings are changed. When compared to other processors, the suggested radar signal processor is inexpensive and small. For the future scope, this paper can be considered as a first step to design a complete radar system with low cost and moderate accuracy according to the other subsystem design such as the antenna and the transceiver.