Abstract
This document describes a numeric pattern for indicating skippable items in data sequences and methods to adjust this pattern when the skippable status for an individual item changes. The pattern provides up to 525% faster iteration speeds (dependent on the ratio of skipped to unskipped items) than an equivalent boolean skipfield on a modern pipelined CPU. This is due to a lack of branching code, reduced number of skipfield reads and a reduced instruction count during iteration, when compared with the boolean pattern. This efficiency is accomplished without significantly impacting the duration taken to change an item’s skippable status. The pattern has significant application in generalized computer science but specifically in the implementation of data containers.
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References
Babka, V., Marek, L., & Tuma, P. (2009). When misses differ: Investigating impact of cache misses on observed performance. In 15th international conference on Parallel and distributed systems (ICPADS), 2009 (pp. 112–119). IEEE.
Bentley, M. R. (2017). Introduction of std::colony to the standard library. www.open-std.org/jtc1/sc22/wg21/docs/papers/2017/p0447r1.pdf.
Bulka, D., & Mayhew, D. (2000). Efficient C++: Performance programming techniques. Boston: Addison-Wesley.
Garcia, J. D., & Stroustrup, B. (2015). Improving performance and maintainability through refactoring in C++ 11. http://www.stroustrup.com/improving_garcia_stroustrup_2015.pdf.
Goldthwaite, L. (2006). Technical report on C++ performance. ISO/IEC PDTR, 18015.
Gregoire, M. (2014). Professional C++. Hoboken: Wiley.
Guyot, A., Hochet, B., & Muller, J. M. (1987). A way to build efficient carry-skip adders. IEEE Transactions on Computers, 36(10), 1144–1152.
Kejariwal, A., Veidenbaum, A. V., Nicolau, A., Tian, X., Girkar, M., Saito, H., et al. (2008). Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel Core 2 Duo processor. In Embedded computer systems: Architectures, modeling, and simulation, SAMOS. Center for embedded computer systems, University of California: Irvine.
Kowarschik, M., & Weiß, C. (2003). An overview of cache optimization techniques and cache-aware numerical algorithms. In U. Meyer, P. Sanders, & J. Sibeyn (Eds.), Algorithms for memory hierarchies: Advanced lectures. Berlin: Springer.
Acknowledgements
I would like to thank both Dr. Gisela Klette of The Auckland University of Technology and Dr. Robert Hurley for their invaluable advice and support in both the critiquing and editing of this document. Also thanks for Steven Cantwell for his advice and Baptiste Wicht for his assistance in building useful benchmarks.
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Bentley, M. The Advanced “Jump-Counting” Skipfield Pattern. Comput Game J 6, 153–169 (2017). https://doi.org/10.1007/s40869-017-0038-3
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DOI: https://doi.org/10.1007/s40869-017-0038-3