Multiobjective optimization and visualization for analog design automation
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Abstract
The automated design of analog and mixedsignal circuits is a wellknown subject of increasing technical and economical significance, e.g., sensory circuits for internet of things, cyberphysical systems, and Industry 4.0.The demand for rapid solution achievement under constraints, as, e.g., robustness, in established and emerging technologies as well as the migration between technologies gives incentive to automation activities. Existing approaches and tools still show improvement potential with regard to multivariate modeling, efficient and multiobjective optimization, as well as transparence and user interaction options during the design. This paper presents new approaches applied within an emerging design environment, denoted as ABSYNTH, with an evolving selflearning architecture for efficient hierarchical optimization in a cascade, which includes function approximators and simulators trained by proven evolutionary optimization algorithms, as well as a novel domainspecific visualization of the optimization space and the trajectory of the design process. Nominal schematiclevel sizing of the commonly used Miller, buffer, and foldedcascode amplifier circuits has been studied with our approach. For Miller, buffer, and foldedcascode, a cascade of harmony search and particle swarm optimization on SVR, ngspice, and cadence simulators was found to be roughly 4 times, 2.5 times, and 2.5 times faster, respectively, than the flat approach with equal or better results. In future work, we will improve the approach by including more demanding circuits, statistical deviations, circuit breeding, advanced optimization, and layout generation.
Keywords
Evolutionary optimization Analog sizing and synthesis ADA Visualization MDS PSO HS SVRIntroduction
The design of integrated circuits and systems, in particular, with analog and mixedsignal units, is a wellknown subject of increasing technical and economical significance. The underlying optimization of the design parameters, from device sizing for established circuits to creation or synthesis of customized or novel circuits, traditionally is executed by experienced human designers, but the issue of analog design automation has been pursued in academia and industry for more than two decades now. The advance of Moore’s law and the increasing complexity and heterogeneity of established and leading edge processes along with increasing robustness and dependability requirements further kindle the interest in efficient analog electronics design automation. In addition to circuit sizing/creation for a new task, also the migration of existing circuit libraries to a new technology is a rewarding task for automation. Adding of statistical, drift, and aging considerations for design centering and yield optimization, including layout synthesis and postlayout simulation results in the loop, can be witnessed from concept to commercial tool level, e.g., in Muneda’s WickED framework [1]. Predominantly, univariate statistical approaches are used, the employed optimization methods are computationally costly, and the design process is rather opaque and lacks interactivity options for the user during the design process.
In our work, we pursue the conception of a modular, multiplatform, and openaccess python system for analog design automation, denoted as Analog Block and system Sizing and sYNTHesis (ABSYNTH) framework. The research goals are the design of an evolving, selflearning architecture for incremental inclusion of cells and knowledge with efficient reuse, to employ wellperforming hierarchical optimization by cascading methods, e.g., SVR and proven workhorses like PSO, and Harmony Search algorithms, during the automated design process, and adding transparence and improved user interaction by domainspecific visualization techniques. The selflearning approach promises to create a perfect balance between speed and low accuracy of function approximation techniques and high accuracy and low speed of the simulationbased techniques, additionally removing the need for massive set of examples required to train the function approximators.
In this paper, well will focus on a threelevel optimization cascade and novel visualization techniques, which are demonstrated for commonly used circuits [2, 3, 4, 5] nominal sizing on schematic level.
In Sect. 2, the stateoftheart is briefly rehearsed. Section 3 describes the baseline of our research and investigation, referring to the previously outlined stateoftheart. Section 4 presents the architecture of the design environment, and Sect. 5 introduces our custom dynamic optimization space visualization. Before concluding, Sect. 7 presents and discusses our experiments and obtained results.
Stateoftheart
Automated analog design automation has been subject of intensive research for the last three decades starting with works like IDAC [6] and OASYS [7]. There are four major approaches to tackle this problem: (1) knowledgebased [6, 8], (2) equationbased [9, 10], (3) simulationbased [11, 12], and (4) modelbased approaches [13, 14] as surveyed in [15]. Each approach has its advantages and disadvantages. The first two approaches require considerable preparatory work for each circuit individually. The substantial time and expertise required for this preparatory work is not alleviating the introduction of more circuits, the growth of the design database, and the corresponding increase in productivity [16]. Simulationbased approaches can be very effective in this regard, however, they consume a lot of computational resources and time, if applied in straight or flat form. With the increase in the speed of computing machinery, this problem is not as significant as it has been a decade ago, but the complexity of the design tasks is also increasing. The fourth approach deals with using regression methods like support vector regression (SVR) and neural networks to create a modelbased equivalent representation as a replacement for simulators and costly detailed simulation runs. Though the modelbased computations are extremely fast, they require careful training and a significant amount of samples selected in a timeconsuming and sensitive process for each circuit and process technology pair to reach an acceptable prediction accuracy [17].
Baseline of investigation
In general, analog sizing and synthesis has been applied to a rich variety of practical circuits, e.g., filters, oscillators, PLLs, amplifiers and comparators, and in part new circuits have been created or evolved by the algorithms. However, in most of the work we refer to, the focus has been on amplifier circuits. Thus, we considered three typical singleended op amp circuits of increasing complexity as a research vehicle for this work. These are a twostage Miller amplifier (MA) [24], threestage buffer amplifier (BA) [24], and a foldedcascode amplifier (FCA). For all these circuits, for each transistor the length was fixed as 1 \(\upmu \)m and the width was chosen as a design parameter. Narrowing down the degrees of freedom by choosing a unit length of all transistors, the number of devices corresponds to the number of optimization parameters. These variables are the parameters that shall be used for the optimization process inside the framework. There is one restriction in the investigations: the passive components are fixed to a typical value and are not yet subject to optimization themselves. The knowledgebased information such as matching information or symmetry constraints for transistor pairs were obtained from the schematic and provided to the systems optimization engine, further reducing the number of parameters.
Circuits
The MA shown in Fig. 1 is taken from [24]. It consists of ten transistors. After symmetry considerations, we optimize eight design parameters, while pursuing ten objectives in the multiobjective approach, as shown in Table 4.
Metaheuristic algorithms

w: Inertia. typ.range: [0, 1].

c1: Cognitive scaling factor. typ. range: [0, 2].

c2: Social scaling factor. typ. range: [0, 2].

r1, r2: Random values between 0 and 1.

Velocity: Particle’s velocity.

Local: Particle’s local best known position.

Global: Swarm’s best known position.

Current: Current position of the particle.

HMS (harmony memory size): problem dependent.

HMCR (harmony memory considering rate): typ.range: [0.7, 0.99].

PAR (pitch adjusting rate): typ range: [0.1, 0.5].
Multiobjective optimization approach
Simulator execution time for one fitness run of Miller amplifier
Simulator  Real execution time (s)  User \(+\) system execution time (s) 

OCN  240  45 
NGS  8  6 
SVR  0.5  0.4 
Execution time for simulators with PSO algorithm on Miller amplifier
Simulator  Real execution time (min)  User \(+\) system execution time (min) 

OCN  395  93 
NGS  15  9 
SVR  20  5 
Time measurement
ABSYNTH concept and architecture
Hybrid multiobjective optimization approach
ABSYNTH concept is shown in Fig. 4. As we have mentioned in Sect. 2, the accuracy vs. speed properties of modelbased and simulatorbased approaches are substantially different, which is illustrated in Fig. 5. The time comparison in running simulations with these methods is provided in Tables 1 and 2. Further, the BSIM3v3 version employed by cadence and ams hitkit is 3.24, while ngspice uses the newer BSIM3v3 version 3.3. This leads to subtle discrepancies in the results, which are not harmful in our hierarchical approach (Fig. 5).
Incrementally evolving selflearning capability
Status of the ABSYNTH architecture’s implementation
Figure 7 shows a block diagram with all the current elements and the building blocks planned in the immediate future of this work.
TRAVISOS: optimization space visualization
The monitoring of the optimization process by visualization means adds transparency to the design process and allows for assessing the quality of the obtained solution [27, 28]. In addition to the conventional cost function over timebased visualizations, as shown in Fig. 8, the optimization space itself and the evolution of the regarded population of optimization solutions can be elucidated by suitable visualization techniques. The underlying problem of optimization space visualization is quite related to the wellknown task of feature space visualization in pattern recognition and intelligent system design [29, 30]. As in these related fields, the highdimensional data, comprised here by the design or sizing parameters in analog circuit and system design automation, have to be subject to a dimensionality reducing mapping, as, e.g., multidimensionalscaling (MDS) and, in particular, nonlinearmapping (NLM) methods, like Sammon’s mapping and its extension to data recall (NLMR) [27, 29, 31]. The application of these methods allow the generation of a lower dimensional, e.g., threedimensional, similarity preserving scatter plot, which will show solution quality and relative location of the solutions. For instance, the latter information allows to understand which regions of the solution space have been explored and what level of diversity is currently maintained by the optimization algorithm. This can naturally be extended from single snapshot monitoring of the optimization process to a complete solution swarm trajectory visualization. As will be shown in the following experimental section, our suggested visualization approach can give numerous salient insights not to be obtained from the conventional cost or progress curve plots. In addition, the approach opens the door to interactive visualization and optimization [28] by allowing selective user manipulations from one population to the next. The proposed new heuristic method for solution swarm trajectory visualization in the regarded optimization space is illustrated in Fig. 2. First, a standard NLM is computed based on the initialization data of the optimization problem. Then, the projections of all swarm elements for the next and all following populations will be computed by the NLMR, which uses the previously obtained results as anchor points. Thus, at low cost successive mappings with smooth transitions of solution locations for the trajectory visualization can be computed. However, it is a wellknown fact that all dimensionality reducing mappings have their problems in terms of displaying an unavoidable mapping error related to the intrinsic dimensionality of the data to be mapped as well as to the employed mapping method itself. This means that solutions with unchanged location in the original design parameter space could see unjustified and disturbing location fluctuations in successive projections.
Summarizing, the TRAVISOS heuristic mapping approach given in Fig. 2 allows the creation of solution swarm trajectory visualization in the regarded optimization space and problem at low to moderate computational cost. This can be employed for transparent analysis and usercentered interactive optimization or designerintheloop optimization, e.g., [27]. The suggested TRAVISOS algorithm and the overall approach are salient for but not limited to the analog sizing and synthesis activities regarded in this work.
Experiments and results
Circuit sizing methods results
Experiment parameters used for experiments in Table 4 and visualizations
PSO  SVR  NGS  OCN 

Num. Par.  20  10  10 
Max. Gen.  1000  1000  10 
Target fitness  Mean < 2  Mean < 0.2  Best \(\le \) 0 
C1  2  2  2 
C2  2  2  2 
Inertia  0.5  0.5  0.5 
Min  1  1  1 
Max  100  100  100 
HS  SVR  NGS  OCN 
Harmony size  20  10  – 
HCMR  0.9  0.9  – 
PAR  0.3  0.3  – 
Max. Iter.  10,000  10,000  – 
Target fitness  Mean < 2  Mean < 0.2  – 
Min  1  1  – 
Max  100  100  – 
Result assessment of hybrid vs. manual and flat approaches
Spec.  Miller amplifier  Foldedcascode amplifier  Buffer amplifier  

Target  Manual  PSO  PPP  HHP  Target  Manual  PSO  PPP  HHP  Target  Manual  PSO  PPP  HHP  
Gain (dB)  70  72.6  73.62  72.15  75.31  60  56.92  67.10  68.17  63.40  50  54  51.10  51.81  50.83 
Std. (dB)  –  –  2.31  2.0  3.16  –  –  2.97  6.78  3.28  –  –  0.72  0.27  0.4 
BW (MHz)  10  18.97  37.60  43.52  43.78  10  52.13  58.45  36.92  39.32  10  27  32.45  19.64  27.11 
Std. (MHz)  –  –  4.75  6.34  8.29  –  –  15  18.4  13.13  –  –  3.6  7.4  11.4 
SR (V/s)  10  60.85  11.26  17.56  18.50  10  54.99  49.53  37.61  24.74  10  14  27.21  18.14  23.36 
Std. (V/s)  –  –  0.74  3.7  6.06  –  –  14.64  1.28  12.6  –  –  3.55  3.73  6.99 
CMRR (dB)  80  77.1  93.39  92.46  92.00  80  90.89  88.25  92.63  90.49  80  80  109.69  109.72  116.52 
Std. (dB)  –  –  0.84  2.63  3.88  –  –  1.29  0.91  4.57  –  –  12.09  10.54  19.49 
Offset (\(\upmu \)V)  1000  0.0114  \(\)92.1  \(\)58.9  \(\)24.7  1000  308  17.5  \(\)215  16.9  1000  \(\)100  \(\)735  \(\)358  \(\)738 
Std. (\(\upmu \)V)  –  –  145  138.34  126.3  –  –  31.9  70.3  257  –  –  200  600  214 
ICMR+ (V)  1  1.42  1.32  1.17  1.27  0.75  0.75  0.75  0.76  0.81  0.45  0.6  0.9  1.05  0.96 
Std. (V)  –  –  0.075  0.106  0.075  –  –  0.001  0.07  0.073  –  –  0.055  0.06  0.12 
ICMR− (V)  –1  \(\)1.54  \(\)1.65  \(\)1.65  \(\)1.65  \(\)0.75  \(\)1.5  \(\)1.50  \(\)1.42  \(\)1.50  \(\)0.45  \(\)0.5  \(\)0.45  \(\)0.45  \(\)0.45 
Std. (V)  –  –  0  0.001  0.001  –  –  0.0  0.0  0.001  –  –  0  0.001  0.0 
OS+ (V)  1  1.52  1.63  1.61  1.62  1  1.64  1.64  1.64  1.64  0.5  0.6  0.63  0.62  0.63 
Std. (V)  –  –  0.007  0.018  0.011  –  –  0.0005  0.003  0.001  –  –  0.005  0.004  0 
OS− (V)  \(\)1  \(\)1.58  \(\)1.63  \(\)1.63  \(\)1.63  \(\)1  \(\)1.64  \(\)1.63  \(\)1.59  \(\)1.60  \(\)0.5  \(\)0.6  \(\)0.53  \(\)0.51  \(\)0.52 
Std. (V)  –  –  0.004  0.012  0.009  –  –  0.0003  0.0001  0.019  –  –  0.009  0.008  0.004 
PD (mW)  2  2.13  1.33  1.51  1.32  1  0.59  0.754  0.702  0.647  2  0.5  1.83  1.42  1.44 
Std. (mW)  –  –  0.44  0.2  0.21  –  –  0.060  0.027  0.008  –  –  0.32  0.3  0.358 
Time (min.)  NA  Days  80  35  21  NA  Days  85  46  30  NA  Days  70  38  27 
Std. (min.)  –  –  25  12.3  4.2  –  –  33  25.1  13.6  –  –  20.2  17.1  7.38 
Visualization methods results
Comparison of different ADA techniques with ABSYNTH
Methods  Equation based  Function approximator based  Simulation based  ABSYNTH 

Speed  High  High  Low  Low, improves with repetitions 
Accuracy  High  Low, improves with examples  High  High 
Preparation effort  High  High  Low  Low 
Human influence for new circuits  Design of equations  100\(+\) examples for learning  Almost nothing  Almost nothing 
Evolution over repetitions  Not possible  Not found  Not possible  Present 
Human computer interface  No research found  No research found  No research found  TRAVISOS, GoalPost view 
First, we regard here the example of the FCA discussed above. Though the conventional visualization given in Fig. 10c is salient, more relevant information can be provided. In Fig. 11, we have visualized snapshots of one particular, tentatively trained SVR results for PPP by TRAVISOS approach. Additionally, we have run a complete simulation using ngspice, merged the two data sets, and visualized the resulting solution space.
From Fig. 10c, we cannot understand the issue, as information on solution diversity, clogging, clustering, or coverage in the optimization space cannot explicitly be extracted. In contrast, TRAVISOS allows this, showing that the SVR model here has not been trained with sufficient data and it is compelled to move towards one, obviously not too fortunate region in the optimization space, while the ngspice results, which have achieved good fitness, are more diverse and spread out into more fortunate regions of the optimization space. The visualization helps to understand the optimization space, as well as the current aptness of SVR training for new cells, and opens the door for interactive optimization.
In Figs. 12, 13, 14, 15, 16 and 17, the entire cascade of the optimization process is visualized by the TRAVISOS method, limiting to a series of representative snapshots here. A complementary video showing the process can be found in [32].
These clearly show the movement of the PSO particles for the SVR model in the optimization space and the evolution of the solution quality. Then, it can be monitored, how these are translated into solutions in the NGS simulations. In the end, we see the final solutions achieved by the OCN.
While the training of the SVR model in general can be understood as a continuing process without a definite termination, the visualization can help to assess whether a sufficient training quality has been achieved. In the investigated case, SVR seems to have been satisfactorily trained, as can be understood from the unchanged solution space for the final result.
This is confirmed by the following simulations steps, since the NGS simulations finish in one generation and OCN reach the target in just three generations.
Summarizing, the TRAVISOS method complements conventional graphical monitoring and assessment techniques of optimization processes. Even the simple examples of the first realization step given here show that salient additional information to better understand and in the future guide the optimization and the underlying design process are provided.
Conclusions
In this paper, we have introduced three novel contributions to the vivid field of electronic design automation for analog and mixedsignal circuits and systems. Inspired by concepts from computational intelligence, we introduced an evolving selflearning architecture that alleviates the introduction of new circuits into the supported cell spectrum, and we introduced and demonstrated a hierarchical multiobjective optimization cascade from SVR, PSO, and HS in the context of this architecture that saves effort in general and is flexible with regard to existing a priori knowledge vs. required computational effort. This approach was demonstrated as part of our emerging ABSYNTH environment together with cadence tools, ngspice and ams AG 0.35 \(\upmu \)m CMOS technology on schematic level for amplifier structures commonly used in related work, but with a more comprehensive set of specification values as optimization goals in an agglomerative approach. Results compared to conventional flat optimization approaches and comparison to manual design activities showed the viability and salience of our approach, e.g., for the best case of the Miller amplifier and HHP as the best variant of our approach, consumed only 26% time of the flat approach, while fully meeting the specifications. A final comparison between the properties and advantages of ABSYNTH to other ADA methods is shown in Table 5.
Further, we introduced a novel visualization method of the optimization space and trajectory (TRAVISOS) that allows more efficient and transparent human supervision of optimization process properties, e.g., diversity and neighborhood relations of solution qualities.
In future work, we will extend the palette of pursued specifications values also to area, etc., take our work to higher level circuits, e.g., instrumentation amplifiers, filters, phaselocked loops, and voltagecontrolled current sources, or even nonlinear circuits, and add statistical, yieldrelated optimization, circuit breeding, as well as physical layout generation, extraction, and inclusion in the optimization loop. In particular, we will also extend our work on the TRAVISOS method moving it from an analysis to an interactive tool, achieving designerintheloop functionality, i.e., letting the designer observe, potentially interfere, and guide the optimization by existing expert knowledge or intuition to faster explore better locations in the optimization space.
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