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A new read–write collision-based SRAM PUF implemented on Xilinx FPGAs

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Abstract

Physically unclonable functions (PUFs) are device-specific digital fingerprints derived from physical properties. They are used in critical cryptographic applications, including unique ID generation, key generation, and challenge-response-based authentication. The advantages of low implementation cost and robust operation render PUF an indispensable component for secure embedded systems. In the last decade, SRAM-based PUFs have become very popular in the ASIC industry due to increasing security demand against cloning and counterfeiting. However, their use in the FPGA applications is limited, since it is almost impossible to power-cycle the SRAMs after the FPGA device is configured. Additionally, FPGA vendors usually clear the SRAM contents after power on which also makes it hard to implement an SRAM PUF. In this work, we propose a new approach for designing SRAM-based PUFs on Xilinx FPGAs. The proposed PUF is based on the idea of triggering a collision between reading and writing operations in a block-RAM to generate random responses induced by timing violation instead of power cycling. We have integrated the proposed PUF as an AXI peripheral with a synthesizable processor core for data acquisition. The design has been tested on 10 different Xilinx Artix-7 devices of the same type, and acquired data were tested for reliability, uniqueness, bit-aliasing, and uniformity properties. On the average, the proposed PUF achieved 93% reliability (at 55 \(^{\circ }\hbox {C}\)), 37% uniqueness, 47% bit-aliasing, and 55% uniformity.

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References

  1. Semiconductor Industry Association, Winning the battle against counterfeit semiconductor products. Tech. Rep. August, Semiconductor Industry Association (2013). https://www.semiconductors.org/clientuploads/Anti-Counterfeiting/SIAAnti-CounterfeitingWhitepaper.pdf

  2. Guajardo, J., Kumar, S.S., Schrijen, G.J., Tuyls, P.: FPGA Intrinsic PUFs and Their Use for IP Protection. In: Paillier, P., Verbauwhede, I. (eds.) Cryptographic Hardware and Embedded Systems - CHES 2007, pp. 63–80. Springer, Berlin Heidelberg, Berlin, Heidelberg (2007)

    Chapter  Google Scholar 

  3. Garg, A., Kim, T.T.: Design of SRAM PUF with improved uniformity and reliability utilizing device aging effect. In: 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1941–1944 (2014)

  4. Mukhopadhyay, D.: PUFs as promising tools for security in internet of things. IEEE Des. Test 33(3), 103 (2016)

    Article  Google Scholar 

  5. Halak, B., Zwolinski, M., Mispan, M.S.: Overview of PUF-based hardware security solutions for the internet of things. In: 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1–4 (2016)

  6. Maes, R.: Physically Unclonable Functions: Constructions, Properties and Applications, 1st edn. Springer-Verlag, Berlin, Heidelberg (2013)

    Book  MATH  Google Scholar 

  7. Liu, M., Zhou, C., Tang, Q., Parhi, K.K., Kim, C.H.: Proceedings of the International Symposium on Low Power Electronics and Design pp. 1–6 (2017)

  8. Gassend, B., Clarke, D., Van Dijk, M., Devadas, S.: Silicon physical random functions. In: Proceedings of the ACM Conference on Computer and Communications Security pp. 148–160 (2002)

  9. Devadas, S., Suh, E., Paral, S., Sowell, R., Ziola, T., Khandelwal, V.: Design and Implementation of PUF-Based “Unclonable” RFID ICs for Anti-Counterfeiting and Security Applications. In: 2008 IEEE International Conference on RFID, pp. 58–64 (2008)

  10. McGrath, T., Bagci, I.E., Wang, Z.M., Roedig, U., Young, R.J.: A PUF taxonomy. Appl. Phys. Rev. 6(1), 011303 (2019)

    Article  Google Scholar 

  11. Selimis, G., Konijnenburg, M., Ashouei, M., Huisken, J., De Groot, H., Van Der Leest, V., Schrijen, G.J., Van Hulst, M., Tuyls, P.: Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes. Proceedings - IEEE International Symposium on Circuits and Systems pp. 567–570 (2011)

  12. Lim, D., Lee, J.W., Gassend, B., Suh, G.E., Van Dijk, M., Devadas, S.: Extracting secret keys from integrated circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 13(10), 1200 (2005)

    Article  Google Scholar 

  13. Suh, G.E., Devadas, S.: Physical unclonable functions for device authentication and secret key generation. In: Proceedings of the 44th annual design automation conference (Association for Computing Machinery, New York, NY, USA), DAC ’07, pp. 9–14 (2007)

  14. Babaei, A., Schiele, G.: Physical unclonable functions in the internet of things: State of the art and open challenges. Sensors (Switzerland) 19(14), (2019)

  15. Maiti, A., Gunreddy, V., Schaumont, P.: A systematic method to evaluate and compare the performance of physical unclonable functions. Embed. Syst. Des. FPGAs 9781461413622, 245 (2013)

  16. Buchovecká, S., Lórencz, R., Kodýtek, F., Buček, J.: True random number generator based on ring oscillator PUF circuit. Microprocess. Microsyst. 53, 33 (2017)

    Article  Google Scholar 

  17. Avaroğlu, E.: The implementation of ring oscillator based PUF designs in Field Programmable Gate Arrays using of different challenge. Phys. A Stat. Mech. Appl. 546, 124291 (2020)

    Article  Google Scholar 

  18. Markettos, A.T., Moore, S.W.: The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators. In: Cryptographic Hardware and Embedded Systems - CHES 2009, ed. by C. Clavier, K. Gaj (Springer Berlin Heidelberg, Berlin, Heidelberg), pp. 317–331 (2009)

  19. Bochard, N., Bernard, F., Fischer, V., Valtchanov, B.: True-randomness and pseudo-randomness in ring oscillator-based true random number generators. Int. J. Reconfig. Comput. 2010, (2010)

  20. Kumar, S.S., Guajardo, J., Maes, R., Schrijen, G., Tuyls, P.: Extended abstract: The butterfly PUF protecting IP on every FPGA. in 2008 IEEE International Workshop on Hardware-Oriented Security and Trust, pp. 67–70 (2008)

  21. Xiao, K., Rahman, M.T., Forte, D., Huang, Y., Su, M., Tehranipoor, M.M.: Bit selection algorithm suitable for high-volume production of SRAM-PUF. In: Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2014 pp. 101–106 (2014)

  22. Holcomb, D.E., Burleson, W.P., Fu, K.: Initial SRAM state as a fingerprint and source of true random numbers for RFID tags. In: Proceedings of the Conference on RFID Security, vol. 58, vol. 58, pp. 1–12 (2007)

  23. Böhm, C., Hofer, M., Pribyl, W.: A microcontroller SRAM-PUF. In: 2011 5th International Conference on Network and System Security, pp. 269–273 (2011)

  24. Barbareschi, M., Battista, E., Mazzeo, A., Mazzocca, N.: Testing 90 nm microcontroller SRAM PUF quality. In: 2015 10th international conference on design technology of integrated systems in nanoscale era (DTIS), pp. 1–6 (2015)

  25. Platonov, M., Hlavác, J., Lórencz, R.: Using power-Up SRAM state of atmel ATmega1284P microcontrollers as physical unclonable function for key generation and chip identification. Inform. Secur. J. A Glob. Perspect. 22(5–6), 244 (2013)

    Article  Google Scholar 

  26. Wild, A., Güneysu, T.: Enabling SRAM-PUFs on Xilinx FPGAs. In: 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp. 1–4 (2014)

  27. Holcomb, D.E., Fu, K.: Bitline PUF: Building Native Challenge-Response PUF Capability into Any SRAM. In: Batina, L., Robshaw, M. (eds.) Cryptographic Hardware and Embedded Systems - CHES 2014, pp. 510–526. Springer, Berlin, Heidelberg (2014)

    Google Scholar 

  28. UG473: Xilinx 7 Series FPGAs Memory Resources User Guide. Xilinx Incorporation, San Jose, CA (2019). https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf

  29. Cherkaoui, A., Fischer, V., Fesquet, L., Aubert, A.: A Very High Speed True Random Number Generator with Entropy Assessment. In: Bertoni, G., Coron, J.S. (eds.) Cryptographic Hardware and Embedded Systems - CHES 2013, pp. 179–196. Springer, Berlin, Heidelberg (2013)

    Chapter  Google Scholar 

  30. Rozic, V., Yang, B., Dehaene, W., Verbauwhede, I.: Highly Efficient Entropy Extraction for True Random Number Generators on FPGAs. In: Proceedings of the 52nd Annual Design Automation Conference (Association for Computing Machinery, New York, NY, USA), DAC ’15 (2015)

  31. Hata, H., Ichikawa, S.: FPGA implementation of metastability-based true random number generator. IEICE Trans. Inform. Syst. E95–D(2), 426 (2012)

    Article  Google Scholar 

  32. Li, D., Lu, Z., Zou, X., Liu, Z.: PUFKEY: a high-security and high-throughput hardware true random number generator for sensor networks. Sensors 15(10), 26251 (2015)

    Article  Google Scholar 

  33. Yamamoto, D., Sakiyama, K., Iwamoto, M., Ohta, K., Ochiai, T., Takenaka, M., Itoh, K.: Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches. In: Preneel, B., Takagi, T. (eds.) Cryptographic Hardware and Embedded Systems - CHES 2011, pp. 390–406. Springer, Berlin, Heidelberg (2011)

    Chapter  Google Scholar 

  34. Chen, S., Li, B., Zhou, C.: FPGA implementation of SRAM PUFs based cryptographically secure pseudo-random number generator. Microprocess. Microsyst. 59, 57 (2018)

    Article  Google Scholar 

  35. Sadr, A., Zolfaghari-Nejad. M.: Physical unclonable function (puf) based random number generator (2012)

  36. Yan, W., Jin, C., Tehranipoor, F., Chandy, J.A.: Phase calibrated ring oscillator PUF design and implementation on FPGAs. In: 2017 27th International Conference on Field Programmable Logic and Applications (FPL), pp. 1–8 (2017)

  37. UG984: Xilinx MicroBlaze Processor Guide. Xilinx Incorporation, San Jose, CA (2019). https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug984-vivado-microblaze-ref.pdf

  38. Usmani, M.: Applications of physical unclonable functions on asics and fpgas. M. eng. thesis, University of Massachusetts Amherst (2018)

  39. Basel, H.: Physically unclonable functions From Basic Design Principles to Advanced Hardware Security Applications. Springer, New York (2018)

    Google Scholar 

  40. Alvarez, A..B.., Zhao, W., Alioto, M.: Static Physically unclonable functions for secure chip identification with 1.9-5.8% native bit instability at 0.6-1 V and 15 fJ/bit in 65 nm. IEEE J. Solid-State Circ. 51(3), 763 (2016)

    Article  Google Scholar 

  41. Lin, L., Srivathsa, S., Krishnappa, D.K., Shabadi, P., Burleson, W.: Design and validation of arbiter-based PUFs for sub-45-nm low-power security applications. IEEE Trans. Inform. Foren. Secur. 7(4), 1394 (2012)

    Article  Google Scholar 

  42. Gu, C., Hanley, N., O’neill, M.: Improved reliability of FPGA-Based PUF identification generator design. ACM Trans. Reconfigurable Technol. Syst. 10(3), (2017)

  43. van der Leest, V., Schrijen, G.J., Handschuh, H., Tuyls, P.: Hardware intrinsic security from D flip-flops. In: Proceedings of the fifth ACM workshop on Scalable trusted computing - STC ’10 (ACM Press), p. 53

  44. Ardakani, A., Baradaran Shokouhi, S.: A secure and area-efficient FPGA-based SR-Latch PUF. In: 2016 8th International Symposium on Telecommunications (IST), pp. 94–99 (2016)

  45. Sedcole, P., K. Cheung, P.Y.: Within-die delay variability in 90nm FPGAs and beyond. In: 2006 IEEE International Conference on Field Programmable Technology, pp. 97–104 (2006)

  46. Cortez, M., Dargar, A., Hamdioui, S., Schrijen, G.: Modeling SRAM start-up behavior for Physical Unclonable Functions. In: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 1–6 (2012)

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Authors and Affiliations

  1. Department of Electrical-Electronics Engineering, Istinye University, Istanbul, Turkey

    Ihsan Cicek

  2. Computer Programming Vocational School, Istinye University, Istanbul, Turkey

    Ahmad Al Khas

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  1. Ihsan Cicek
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Cicek, I., Al Khas, A. A new read–write collision-based SRAM PUF implemented on Xilinx FPGAs. J Cryptogr Eng 13, 19–36 (2023). https://doi.org/10.1007/s13389-021-00281-8

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