Abstract
In the present work, the authors have studied the Quasi-Static Capacitance–Voltage (QSCV) characteristics of 10 nm gate length double gate (DG) NMOSFETs of different channel materials namely, Si, Ge, and \({In}_{0.53}G{a}_{0.47}As\), the results are reported using Silvaco ATLAS TCAD. The QSCV approach provides the advantage of immunity against frequency-dependent effects and has the ability to measure the small capacitance in the range of 100 fF. In this device, we consider the self-consistent solution of Schrodinger’s equation with Poisson’s equation. Further, the conduction band splitting in multiple sub-bands has been considered with light doping in the channel region. For this, the authors have studied C-V behaviour of the devices by observing the effect of metal gate work function engineering (using Ta, W, Mo, Ni, Au and Pt), channel engineering (using Si, \({{\text{In}}}_{0.53}{{\text{Ga}}}_{0.47}{\text{As}}\) and Ge) and variation of channel thickness (2 nm, 5 nm, 10 nm and 1502 nm) with gate oxide \((Si{O}_{2})\) of thickness 1.2 nm. In further studies, \(Si{O}_{2}\) was replaced its EOT with \(Hf{O}_{2}\) and results were again studied. The comparison of the behavior of C-V curve has been done for the above-mentioned channel materials. It was found that there is a significant reduction in inversion mode Capacitance with voltage for all the channel materials used for both SiO2 based devices and with HfO2 based devices. This has been attributed to quantization which results in a decrease in the overall gate to channel capacitance (CGC) and hence increases the threshold voltage in MOS device. The quantization effect is lightly seen in Si for channel thickness of 2 nm, however for the same thickness, quantization is seen in Ge. Also for In0.53Ga0.47As quantization is seen for channel thickness of 2nm, 5nm, and 10 nm because of its low electron effective mass. The QSCV characteristics are also used to measure oxide thickness, flat-band voltage, threshold voltage, maximum depletion region thickness, distribution of charges in dielectric, interface traps charge and interface states between channel and gate oxide before fabrication of the device.
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18 April 2024
A Correction to this paper has been published: https://doi.org/10.1007/s12633-024-02955-4
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One of the authors, Sanjay, acknowledges the financial support in form of SRF from the University Grants Commission (UGC), New Delhi, India.
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The work has been done in collaborative manner with the authors collectively conceptualising the idea of the work including the structure of the device. Dr. Sanjay who specialises in simulation on Silvaco, took up the work on setup of the devices on the simulator and ran the simulations. Dr. Vibhor Kumar along with Dr. Sanjay created the various viewgrams and the results in the present form. The work was mainly done in the laboratory of Dr. Anil Vohra who brought out the novelty of the work that helped to complete the article in its present form.
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Sanjay, Kumar, V. & Vohra, A. Quantization Effect in N-Channel Inversion Mode Si, In0.53Ga0.47As and Ge Based Double Gate MOSFET Using Quasi-Static Capacitance–Voltage Characteristics for Upcoming Sub 10 nm Technology Node. Silicon (2024). https://doi.org/10.1007/s12633-024-02919-8
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DOI: https://doi.org/10.1007/s12633-024-02919-8